{"title":"用于以太网DFE的VLSI架构优化","authors":"Wang Xuejing, Ye Fan, R. Junyan","doi":"10.1109/ICASIC.2005.1611261","DOIUrl":null,"url":null,"abstract":"An optimum design of decision feedback equalizer (DFE) used in Ethernet is presented. This paper proposes two improving measures for physical implementation - the hybrid form and the coefficient updating unit sharing. According to the results of synthesis using SMIC, 0.18/spl mu/m CMOS process, the speed, area and power consumption of the improved DFE is optimized by 16%, 36% and 39% compared with the transposed form implementation.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"24 3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An optimization of VLSI architecture for DFE used in Ethernet\",\"authors\":\"Wang Xuejing, Ye Fan, R. Junyan\",\"doi\":\"10.1109/ICASIC.2005.1611261\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An optimum design of decision feedback equalizer (DFE) used in Ethernet is presented. This paper proposes two improving measures for physical implementation - the hybrid form and the coefficient updating unit sharing. According to the results of synthesis using SMIC, 0.18/spl mu/m CMOS process, the speed, area and power consumption of the improved DFE is optimized by 16%, 36% and 39% compared with the transposed form implementation.\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"24 3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611261\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611261","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
提出了一种用于以太网的决策反馈均衡器的优化设计方法。本文提出了物理实现的两种改进措施——混合形式和系数更新单元共享。根据采用中芯0.18/spl μ m CMOS工艺合成的结果，改进后的DFE与转置形式实现相比，速度、面积和功耗分别优化了16%、36%和39%。
An optimization of VLSI architecture for DFE used in Ethernet
An optimum design of decision feedback equalizer (DFE) used in Ethernet is presented. This paper proposes two improving measures for physical implementation - the hybrid form and the coefficient updating unit sharing. According to the results of synthesis using SMIC, 0.18/spl mu/m CMOS process, the speed, area and power consumption of the improved DFE is optimized by 16%, 36% and 39% compared with the transposed form implementation.
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