RTL satisfiability solving using an ATPG based approach

Abstract

We present a special approach to solving satisfiability problem in RTL (register transfer level) circuit, which contains both Boolean logics and word-level arithmetics. In our approach, an ATPG (automatic test pattern generation) based satisfiability solver is implemented on RTL netlist model. As expert tool for circuits, our ATPG engine employs fast constraint propagation, where all the signals are treated as integers. For the undecided signals, we render a depth-first search. The huge search space is cut down by some heuristics. Experimental results on ITC benchmarks demonstrate the feasibility and efficiency of our techniques.