A novel asynchronous multiple function multiply-accumulator

Abstract

The paper describes a 16-bit high-speed and low-power multiply-accumulate unit (MAC) designed for DSP processor. The extreme power reduction derives from the asynchronous interlocked pipeline technique MAC adopts. And the speed is greatly increased by introducing the complemented partial product word correction (CP-PWC) algorithm and 3D reduction method (TDM) in the partial product generation and reduction. MAC shows low power dissipation and high speed and the DSP processor embedded with MAC has been implemented in 0.18 CMOS technology.