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2005 IEEE Conference on Electron Devices and Solid-State Circuits最新文献

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Charge Collection in Impact Ionization MOS Transistors 冲击电离MOS晶体管中的电荷收集
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635371
W. Wang
{"title":"Charge Collection in Impact Ionization MOS Transistors","authors":"W. Wang","doi":"10.1109/EDSSC.2005.1635371","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635371","url":null,"abstract":"Single Event Upset is listed as one of the major challenges for further scaled devices by ITRS. For any newly proposed device, it is very important to study the potential robustness against single event upset. The charge collection is the fundamental parameter to determine the device radiation hardness. In this paper, 2-D device simulations were performed to study the charge collection in impact ionization MOS devices. The charge collection dependencies on high energy particle strike location as well as different bias conditions have been investigated. Unlike in conventional SOI CMOS device, little charge amplification effect was observed in this emerging new device.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126179799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Full Swing And Low Power Voltage-Controlled Ring Oscillator 一种全摆幅低功率压控环形振荡器
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635226
Xin Wu, Dunshan Yu, Shimin Sheng
{"title":"A Full Swing And Low Power Voltage-Controlled Ring Oscillator","authors":"Xin Wu, Dunshan Yu, Shimin Sheng","doi":"10.1109/EDSSC.2005.1635226","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635226","url":null,"abstract":"This paper presents a full swing and low power Voltage Controlled Ring Oscillator fabricated in a 0.35um CMOS technology. The VCO delay cell utilizes a nmos delay pair to save the power dissipation while degrading the phase noise a little.the proposed VCO has a wide tuning range from 450MHz to 1.15GHz with a good linearity. The phase noise is -106dBc/Hz at 500 KHz offset from the center frequency of 866MHz and it consumes 24.5mW using a 3.3V power supply. The area of VCO is 131 x 30.8 μm2.A PLL with the proposed VCO is also implemented and the rms cycle-to-cycle jitter is 4.34ps.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129712135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Monitoring of Switching Activity and Transition Times of Clock Signals in SoC Cells by Estimation of the Mean Value of IDD Current 利用IDD电流的平均值监测SoC电池中时钟信号的开关活动和转换时间
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635384
P. Dziurdzia
{"title":"Monitoring of Switching Activity and Transition Times of Clock Signals in SoC Cells by Estimation of the Mean Value of IDD Current","authors":"P. Dziurdzia","doi":"10.1109/EDSSC.2005.1635384","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635384","url":null,"abstract":"In the paper an idea of monitoring of System on Chips operation by estimation of the mean value (MV) of IDDcurrent (IDDMV) in SoC cells is shown. A special monitoring unit of the MV of the IDDcurrent is presented as well as results of simulations relating to monitoring of switching activity and transitions times of clock signals in exemplary SoC cells designed in 0.35μm technology. Following up of the MV of the IDDcurrent in individual cells of a given SoC seems to be an universal way of testing of mixed circuits, leading in consequence to increased reliability and production yield.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128344958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Opportunistic Source Line Driving Scheme for Low Power Mobile TFT-LCD Driver IC 低功耗移动TFT-LCD驱动IC的机会源线驱动方案
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635335
Jae-Goo Lee, J. Woo, B. Kong, Young-Hyun Jun, Chil-Gee Lee, I. Kang, Bongnam Kim, Jin-Tae Kim
{"title":"An Opportunistic Source Line Driving Scheme for Low Power Mobile TFT-LCD Driver IC","authors":"Jae-Goo Lee, J. Woo, B. Kong, Young-Hyun Jun, Chil-Gee Lee, I. Kang, Bongnam Kim, Jin-Tae Kim","doi":"10.1109/EDSSC.2005.1635335","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635335","url":null,"abstract":"An opportunistic source line driving (OSLD) scheme is proposed for use in mobile TFT_LCD driver ICs (T-LDIs). In OSLD scheme, the operation of the source drivers of a T-LDI is controlled by the equivalence of RGB color data for adjacent pixels. That is, one source driver drives the neighboring source lines as well as the corresponding one when the color data of adjacent pixcels are identical to each other. With this scheme, all the source drivers associated with the neighboring source lines can be completely turned off, allowing the reduction of static and dynamic current of these drivers. Test chip was fabricated in a 5-V/0.8-um 2.5V/0.25-um triple-metal CMOS process, and the experimental result shows that the power reduction of 12% ~ 21% was obtained with die size overhead less than 0.5%.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127166347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An InGaP/GaAs HBT MMIC Power Amplifier with an Integrated Diode Linearizer 带集成二极管线性化器的InGaP/GaAs HBT MMIC功率放大器
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635239
M. Zhu, H. Yang, H.Y. Zhang, X.C. Liu
{"title":"An InGaP/GaAs HBT MMIC Power Amplifier with an Integrated Diode Linearizer","authors":"M. Zhu, H. Yang, H.Y. Zhang, X.C. Liu","doi":"10.1109/EDSSC.2005.1635239","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635239","url":null,"abstract":"An InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) power amplifie (PA) using an improved linearization technique is studied in this paper. This improved linearization technique provides high efficiency at different amplification ofthe modulation as well as high operation voltage. Also the gain compression and the phase distortion of the HBT are effectively improved with no additional DC consumption. The fabricated HBT MMIC PA exhibits an output power of 24 dBm and a power-added efficiency as high as 37% at an operation voltage of6.5 V.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130080757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of oxidation temperature on Ga2O3film thermally grown on GaN 氧化温度对ga2o3薄膜在GaN上热生长的影响
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635346
Limin Lin, Yi Luo, P. Lai, K. Lau
{"title":"Effects of oxidation temperature on Ga2O3film thermally grown on GaN","authors":"Limin Lin, Yi Luo, P. Lai, K. Lau","doi":"10.1109/EDSSC.2005.1635346","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635346","url":null,"abstract":"The effects of oxidation temperature on thermally oxidized GaN film were investigated. The GaN wafers were oxidzied at 750°C, 800°C and 850°C respectively. The electrical characteristics and interface quality of MOS capacitors were compared among different oxidation temperatures. The sample oxidized at 800°C presented best current-voltage, capacitance-voltage characteristics and smoothest surface morphology, while the higher oxidation temperature of 850°C gave best interface quality. The electrical breakdown field was increased by one order of magnitude when the sample was oxidized at 800°C as compared with 750°C and 850°C. Lastly, after the sample oxidized at 800°C was annealed at 850°C for 10 min, the quality of its oxide was significantly degraded.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123159472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A TDI CMOS Readout Circuit for IRFPA with Linearity Improvement 一种线性度改进的红外平面放大器TDI CMOS读出电路
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635342
Zhang Ya-cong, Liu Dan, Lu Wengao, Chen Zhongjian, Ji Lijiu, Zhao Baoying
{"title":"A TDI CMOS Readout Circuit for IRFPA with Linearity Improvement","authors":"Zhang Ya-cong, Liu Dan, Lu Wengao, Chen Zhongjian, Ji Lijiu, Zhao Baoying","doi":"10.1109/EDSSC.2005.1635342","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635342","url":null,"abstract":"This paper presents a readout integrated circuit (ROIC) for infrared focal plane array (IRFPA) with time delay and integration (TDI) mode suitable for CMOS technology. The unit-cell input stage is implemented with switch current integration (SCI) structure with a simple linearity improvement circuit. The current flowing out of the unit-cell is directed to the off-pixel integration capacitors through a switch array. The signals from different detectors for the same image pixel are stored on the same capacitor, implementing the summation function. The voltage signals on capacitors are read out serially after they pass through the correlated double sample stage. Defective pixel correction is also implemented in this circuit. The simulation results show that the TDI function is correctly implemented and the linearity is improved from 96.15% to 97.70% (without the common output stage) at the expense of a little increase of power dissipation.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126090573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dimensional and Other New Effects in Advanced SOI Devices 先进SOI器件中的维度效应和其他新效应
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635209
Sorin Cristoloveanu
{"title":"Dimensional and Other New Effects in Advanced SOI Devices","authors":"Sorin Cristoloveanu","doi":"10.1109/EDSSC.2005.1635209","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635209","url":null,"abstract":"Institut de Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG & UJF), ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France. E-mail: sorin@enserg.fr Abstract-The principles of SOI technology for ultimate scaling are reviewed. Several interesting mechanisms result from the reduction in the transistor volume or from the implementation of several gates. The discussion is based on recent measurements in advanced SOI MOSFETs.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115222239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Parasitic Minimization in RF Multi-Fin FETs 射频多鳍场效应管中的寄生最小化
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635272
Wen Wu, Zhikuan Zhang, M. Chan
{"title":"Parasitic Minimization in RF Multi-Fin FETs","authors":"Wen Wu, Zhikuan Zhang, M. Chan","doi":"10.1109/EDSSC.2005.1635272","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635272","url":null,"abstract":"This paper studies the minimization of parasitics in multi-fin MOS devices. A distributed RC model is provided to minimize the gate resistances and the influence of device geometrical parameters on gate RC delay is thoroughly investigated. Also, we give a criterion to achieve the minimal gate resistance for RF device design. Furthermore, methods of reducing source/drain parasitic resistances and capacitances are discussed.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115791310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Fully Integrated SiGe Low Noise Amplifier for 3-5GHz Ultra-WideBand Radio 用于3-5GHz超宽带无线电的全集成SiGe低噪声放大器
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635250
Li Yang, H. Liao, Guoyan Zhang, Ru Huang, Xing Zhang
{"title":"A Fully Integrated SiGe Low Noise Amplifier for 3-5GHz Ultra-WideBand Radio","authors":"Li Yang, H. Liao, Guoyan Zhang, Ru Huang, Xing Zhang","doi":"10.1109/EDSSC.2005.1635250","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635250","url":null,"abstract":"A fully integrated low-frequency band (3.1-5 GHz) UWB LNA was designed and implemented with Jazz 0.35μm SiGe BiCMOS (peak fT60 GHz) process. The measured maximum power gain is 15.7 dB at 3.5 GHz with 0.6dB gain flatness over the whole operating bandwidth. And the minimum noise figure 3.8 dB is achieved at 4GHz. The whole circuit including the bias circuit network consumes 7mA with 3V supply and only occupies 0.65 mm x 0.9mm.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133171910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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