{"title":"射频多鳍场效应管中的寄生最小化","authors":"Wen Wu, Zhikuan Zhang, M. Chan","doi":"10.1109/EDSSC.2005.1635272","DOIUrl":null,"url":null,"abstract":"This paper studies the minimization of parasitics in multi-fin MOS devices. A distributed RC model is provided to minimize the gate resistances and the influence of device geometrical parameters on gate RC delay is thoroughly investigated. Also, we give a criterion to achieve the minimal gate resistance for RF device design. Furthermore, methods of reducing source/drain parasitic resistances and capacitances are discussed.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Parasitic Minimization in RF Multi-Fin FETs\",\"authors\":\"Wen Wu, Zhikuan Zhang, M. Chan\",\"doi\":\"10.1109/EDSSC.2005.1635272\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper studies the minimization of parasitics in multi-fin MOS devices. A distributed RC model is provided to minimize the gate resistances and the influence of device geometrical parameters on gate RC delay is thoroughly investigated. Also, we give a criterion to achieve the minimal gate resistance for RF device design. Furthermore, methods of reducing source/drain parasitic resistances and capacitances are discussed.\",\"PeriodicalId\":429314,\"journal\":{\"name\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2005.1635272\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2005.1635272","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper studies the minimization of parasitics in multi-fin MOS devices. A distributed RC model is provided to minimize the gate resistances and the influence of device geometrical parameters on gate RC delay is thoroughly investigated. Also, we give a criterion to achieve the minimal gate resistance for RF device design. Furthermore, methods of reducing source/drain parasitic resistances and capacitances are discussed.