{"title":"先进SOI器件中的维度效应和其他新效应","authors":"Sorin Cristoloveanu","doi":"10.1109/EDSSC.2005.1635209","DOIUrl":null,"url":null,"abstract":"Institut de Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG & UJF), ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France. E-mail: sorin@enserg.fr Abstract-The principles of SOI technology for ultimate scaling are reviewed. Several interesting mechanisms result from the reduction in the transistor volume or from the implementation of several gates. The discussion is based on recent measurements in advanced SOI MOSFETs.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Dimensional and Other New Effects in Advanced SOI Devices\",\"authors\":\"Sorin Cristoloveanu\",\"doi\":\"10.1109/EDSSC.2005.1635209\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Institut de Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG & UJF), ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France. E-mail: sorin@enserg.fr Abstract-The principles of SOI technology for ultimate scaling are reviewed. Several interesting mechanisms result from the reduction in the transistor volume or from the implementation of several gates. The discussion is based on recent measurements in advanced SOI MOSFETs.\",\"PeriodicalId\":429314,\"journal\":{\"name\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE Conference on Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2005.1635209\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2005.1635209","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Dimensional and Other New Effects in Advanced SOI Devices
Institut de Microelectronics, Electromagnetism and Photonics (UMR CNRS, INPG & UJF), ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France. E-mail: sorin@enserg.fr Abstract-The principles of SOI technology for ultimate scaling are reviewed. Several interesting mechanisms result from the reduction in the transistor volume or from the implementation of several gates. The discussion is based on recent measurements in advanced SOI MOSFETs.