Parasitic Minimization in RF Multi-Fin FETs

Abstract

This paper studies the minimization of parasitics in multi-fin MOS devices. A distributed RC model is provided to minimize the gate resistances and the influence of device geometrical parameters on gate RC delay is thoroughly investigated. Also, we give a criterion to achieve the minimal gate resistance for RF device design. Furthermore, methods of reducing source/drain parasitic resistances and capacitances are discussed.