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2005 IEEE Conference on Electron Devices and Solid-State Circuits最新文献

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Investigation of Z-shaped Photoluminescence of Exciton in ZnO Single-crystal Microtubes ZnO单晶微管中激子z形光致发光的研究
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635313
N. Liu, Y. R. Li, LH. Deng, Y. S. Sun, X. Zhou, H. J. Wu
{"title":"Investigation of Z-shaped Photoluminescence of Exciton in ZnO Single-crystal Microtubes","authors":"N. Liu, Y. R. Li, LH. Deng, Y. S. Sun, X. Zhou, H. J. Wu","doi":"10.1109/EDSSC.2005.1635313","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635313","url":null,"abstract":"The photoluminescence properties of ZnO single-crystal microtubes grown on Si substrate by hydrothermal method were investigated. An anomalous Z-shaped red-shift was found in the photoluminescence spectra, implying a new temperature switch characteristics. These results are considered to be from the competition among three kinds of excitons, which are localized excitons due to trapping in the intrinsic impurities and interface states at low temperatures; localized excitons and bound from thermally activated and transferred into bound states at intermediate temperatures; and, free excitons and unknown exciton complexes by thermal energy (kT) transfer part of the bound excitons into free excitons at high temperatures. As a result, free excitonsand interface states-excitons strongly overlaped.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133725029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Heterostructure PIN Rectifier Diode For Power Applications 电源应用异质结构PIN整流二极管
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635400
B. Mazhari, M. Sinha, J. Dixit
{"title":"Heterostructure PIN Rectifier Diode For Power Applications","authors":"B. Mazhari, M. Sinha, J. Dixit","doi":"10.1109/EDSSC.2005.1635400","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635400","url":null,"abstract":"We propose use of heterostructures in PIN rectifiler diodes for obtaining faster switching speed. It is shown that by employing a small bandgap material in the heavily doped P layer and a wide bandgap material in the intrinsic region, reverse recovery time can be significantly lowered without compromising either the breakdown or the forward ON voltage.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Complete Carrier-Based Non-Charge-Sheet Analytic Model for Nano-Scale Undoped Symmetric Double-Gate MOSFETs 纳米尺度非掺杂对称双栅mosfet的完整载流子非电荷片分析模型
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635253
Jin He, Zhang Xing, Yangyuan Wang
{"title":"A Complete Carrier-Based Non-Charge-Sheet Analytic Model for Nano-Scale Undoped Symmetric Double-Gate MOSFETs","authors":"Jin He, Zhang Xing, Yangyuan Wang","doi":"10.1109/EDSSC.2005.1635253","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635253","url":null,"abstract":"A complete carrier-based non-charge-sheet analytic model for nano-scale undoped symmetric doublegate MOSFETs is presented in this paper. The formulation is based on the Poisson's equation to solve for the carrier (electron) concentration directly rather than relying on the surface potential alone. Therefore, the distribution of the potential, the field, and the charge density in the channel away from the surface is also expressed in terms of the carrier concentration, giving a complete carrier-based noncharge-sheet model for nano-scale undoped symmetric double-gate MOSFETs including the short-channel effects. The model formulation has an analytic form that does not need to solve for the transcendent equation as in the conventional surface potential model or classical Pao-Sah formulation. As a result, the model can analytically predict the analytical I-V and C-V characteristics of the undoped symmetric double-gate MOSFETs. The validity of the model results has also been demonstrated by the extensive comparison with the 2-D numerical simulation and experimental data.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134536734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Realization of an Integrated Planar LC Low-Pass Filter with Modified Surface Micromachining Technology 改进表面微加工技术的集成平面LC低通滤波器的实现
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635379
J. Fang, Z.W. Liu, Z.M. Chen, L.T. Liu, Z.J. Li
{"title":"Realization of an Integrated Planar LC Low-Pass Filter with Modified Surface Micromachining Technology","authors":"J. Fang, Z.W. Liu, Z.M. Chen, L.T. Liu, Z.J. Li","doi":"10.1109/EDSSC.2005.1635379","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635379","url":null,"abstract":"An Integrated Planar LC LPF(Low-Pass Filter) is designed and fabricated with Modified Surface Micromachining. The LPF is accomplished on low-resistance silicon substrate. To increase the performance of the filter, the substrate underneath the devices is modified with OPS (oxided porous silicon) technology. Measurement results give -3dB bandwidth of 2.925GHz and midband insertion loss of 0.874dB at 500MHz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133069686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Fully Balanced Fifth-Order Low-Pass Chebyshev Filter Based On Quasi-Floating Gate Transistors 基于准浮栅晶体管的全平衡五阶低通切比雪夫滤波器
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635327
Bao-jun Zhang, Yin-Tang Yang, Hai-jun Zhang
{"title":"A Fully Balanced Fifth-Order Low-Pass Chebyshev Filter Based On Quasi-Floating Gate Transistors","authors":"Bao-jun Zhang, Yin-Tang Yang, Hai-jun Zhang","doi":"10.1109/EDSSC.2005.1635327","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635327","url":null,"abstract":"A CMOS fully differential integrator based on quasi-floating gate technique is proposed. Its detailed structure, transfer characteristic and integral performance are analyzed. Using the integrator circuit, a fully balanced fifth-order Chebyshev low-pass filter, which have a 2MHz cutoff frequency and 346.1μW power dissipation, is designed by the RLC ladder simulation method. Theoretical analysis and the feasibility of the filter have been verified by the simulation results.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133371440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Numerical Simulation of Negative Differential Resistance Characteristics in Si/Si1-χGeχRTD at Room Temperature 室温下Si/Si1-χGeχRTD负差分电阻特性的数值模拟
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635293
Tao Li, Zhiping Yu, Yan Wang, Lei Huang, Cailan Xiang
{"title":"Numerical Simulation of Negative Differential Resistance Characteristics in Si/Si1-χGeχRTD at Room Temperature","authors":"Tao Li, Zhiping Yu, Yan Wang, Lei Huang, Cailan Xiang","doi":"10.1109/EDSSC.2005.1635293","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635293","url":null,"abstract":"Negative differential resistance (NDR) characteristics in the current-voltage curve of a p-type Si/Si1-χGeχresonant tunnelling diode (RTD) are simulated with the quantum hydrodynamic (QHD) model. An integrated difference scheme including Schafetter-Gummel (SG) method, second upwind method and second-order central difference method is used to discretize the QHD equations, which maintains both accuracy and stability. This work is the first to simulate hole transport in RTD using the QHD model. Investigations of some structure modifications have been carried out. Analysis of the results indicates that both quantum barrier thickness and hole effective mass have an impact on NDR characteristics for Si/Si1-χGeχRTD. The simulated peak-to-valley current ratio (PVCR) of 1.14 at T=293K agrees quantitatively with the experimental result when x=0.23.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117177496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Implementation of Perfect-Magnetic-Coupling Ultra-Low-Loss Transformer in Standard RFCMOS Technology 完美磁耦合超低损耗变压器在标准RFCMOS技术中的实现
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635300
Yo‐Sheng Lin, Hsiao-Bin Liang, Yan-Ru Tzeng
{"title":"Implementation of Perfect-Magnetic-Coupling Ultra-Low-Loss Transformer in Standard RFCMOS Technology","authors":"Yo‐Sheng Lin, Hsiao-Bin Liang, Yan-Ru Tzeng","doi":"10.1109/EDSSC.2005.1635300","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635300","url":null,"abstract":"In this paper, we propose a single-turn multiple-layer interlaced stacked transformer structure with nearly perfect magnetic-coupling factor (kIM∼ 1) using standard mixed-signal/RF CMOS (or BiCMOS) technology. A single-turn six-layer interlaced stacked transformer was implemented to demonstrate the proposed structure. Temperature dependence (from -25 °C to 175°C) of the quality-factor (Q-factor), kIm, resistive-coupling factor (kRe), maximum available power gain (GAmax), and minimum noise figure (NFmin) performances of the transformer are reported. State-of-the-art GAmaxof 0.762 and 0.904 (i.e. NFminof 1.181 dB and 0.437 dB) have been achieved at 5.2 GHz and 8 GHz, respectively, at room temperature, mainly due to the perfect magnetic-coupling factor and the high resistive-coupling factor. The present analysis is helpful for RF engineers to design ultra-low-voltage high-performance transformer-feedback LNAs and VCOs, and other RF-ICs which include transformers.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Integration Design of Chip and Package for Cost-Effective High-Speed Applications 高性价比高速应用的芯片与封装集成设计
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635350
N. Chen, Hongchin Lin, N. Chen, R. Wu, T. Chou, H. Chien
{"title":"Integration Design of Chip and Package for Cost-Effective High-Speed Applications","authors":"N. Chen, Hongchin Lin, N. Chen, R. Wu, T. Chou, H. Chien","doi":"10.1109/EDSSC.2005.1635350","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635350","url":null,"abstract":"Low cost is the trend for consumer electronics. However, the challenges of the LCD-TV processor using cost-effective two-layer ball grid array (BGA) packages suffer from serious crosstalk and return loss due to lack of a solid plane to suppress the coupling effect and control the trace impedance. Two types of two-layer BGA packages were measured and simulated using a 3D full-wave electromagnetic field solver and an EM-based 3D parasitic extractor to analyze their speed limitations and power coupling between the signals and the power net. The results indicated the signal coupling is the dominant factor for insertion loss. Thus, the design guidelines and specifications using two-layer BGA packages are proposed for development of the next generation processors.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115354797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Polymer and Small Molecules Light Emitting Diodes - A Technology for Large Area Low Information Contents Displays 聚合物和小分子发光二极管——一种用于大面积低信息量显示的技术
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635314
R. Anand, A. Giri, R. Prasad
{"title":"Polymer and Small Molecules Light Emitting Diodes - A Technology for Large Area Low Information Contents Displays","authors":"R. Anand, A. Giri, R. Prasad","doi":"10.1109/EDSSC.2005.1635314","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635314","url":null,"abstract":"Polymer Light Emitting Diodes (PLEDs) and Organic Light Emitting Diodes (OLEDs) have made great progress in terms of efficiency, brightness and lifetimes during its last few years of development. The technology looks mature enough to produce real commercial products like high-resolution flat panel displays for cell phones, computers and televisions. However, it is also quite promising for low information content displays. In this work, the technology of low information content displays like 7-segment and simple billboard type of displays using polymer and small molecules has been developed. The processes, structures, characteristics and advantages of OLEDsand PLEDs over LCDs and inorganic LEDs are presented.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis and Design of Voltage Controlled Current Source for LDO Frequency Compensation LDO频率补偿压控电流源的分析与设计
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635282
Qiang Bian, Zushu Yan, Yuanfu Zhao, S. Yue
{"title":"Analysis and Design of Voltage Controlled Current Source for LDO Frequency Compensation","authors":"Qiang Bian, Zushu Yan, Yuanfu Zhao, S. Yue","doi":"10.1109/EDSSC.2005.1635282","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635282","url":null,"abstract":"Using voltage controlled current source (VCCS) instead of electrical series resistance (ESR) of load capacitor to create a zero is a novel LDO frequency compensation scheme. This paper analyzes this compensation scheme, and reveals that the VCCS circuit conduces to the improvements of transient response and PSR performance of LDO. A new area compact VCCS circuit that has a nearly ideal performance in wide frequency spectrum up to 5MHzis also presented. Using VCCS, a LDO with 300mV dropout, 2.5V output voltage and l00mA output current is designed in 0.5μm CMOS technology with pretty frequency performance, transient response and PSR performance. The total on-chip capacitor employed in this LDO is less than 1pF.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123589690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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