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2005 IEEE Conference on Electron Devices and Solid-State Circuits最新文献

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Technology Platform Based On Comprehensive Device Modeling For RF SoC Design 基于综合器件建模的射频SoC设计技术平台
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635199
Yuhua Cheng
{"title":"Technology Platform Based On Comprehensive Device Modeling For RF SoC Design","authors":"Yuhua Cheng","doi":"10.1109/EDSSC.2005.1635199","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635199","url":null,"abstract":"As the semiconductor industry continually drives our life into 21st century with increased productivity and improved convenience throughout the economy, both foundries and EDA vendors are heavily investing in developing the technology platform for nano-scale and RF technologies, in order to support the significantly increased demand for compact, low cost, and low power IC design. With a lot of fundamentals to be understood and a lot of technical barriers to be overcome in process technologies, device modeling advanced design methodologies, and system architecture, this technology platform is becoming crucial in providing an accurate and efficient design environment for RF SoC design. This paper will try to outline this technology platform and review in general device modeling and its role as a foundation of the advanced technology platform for RF SoC design.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114075526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Power and Hardware Efficient Decimation Filters in Sigma-Delta A/D Converters Sigma-Delta A/D转换器中的低功耗和硬件高效抽取滤波器
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635362
Hengfang Zhu, Xiaobo Wu, Xiaolang Yan
{"title":"Low-Power and Hardware Efficient Decimation Filters in Sigma-Delta A/D Converters","authors":"Hengfang Zhu, Xiaobo Wu, Xiaolang Yan","doi":"10.1109/EDSSC.2005.1635362","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635362","url":null,"abstract":"The power and area formulas for four popular Sinc-filter structures used in decimation filters were discussed in this paper. It was proved that the formulas are very useful in power or area estimation and comparison. The circuit implementations of each structure are illustrated. And the power and area comparisons of the four structures were simulated and analyzed. A further optimization technology for one of the efficient filter structures was also proposed.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122895297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Orientation-Dependent Energy Bandstructure Calculation for Silicon Nanowires Using Supercell Approach with the Tight-Binding Method 基于紧密结合方法的硅纳米线方向相关能带结构计算
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635195
X. Guan, Zhiping Yu
{"title":"Orientation-Dependent Energy Bandstructure Calculation for Silicon Nanowires Using Supercell Approach with the Tight-Binding Method","authors":"X. Guan, Zhiping Yu","doi":"10.1109/EDSSC.2005.1635195","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635195","url":null,"abstract":"The Tight-Binding (TB) model has been applied to investigate the bandstructures for semiconductor nanowires. With a specific implementation of SP3d5s* in the TB method, the orientation dependence of nanowire bandstructures can be quickly and accurately evaluated. It is found that while most axial directions of nanowires preserve the indirect band gap of bulk silicon, particular orientation can render direct band gap feature. In this paper, a [112] oriented silicon nanowire has been simulated using supercell approach and compared to the available measured data. The good agreement shows the proposed method is highy reliable and efficient.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125559269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Fast-settling Temperature-Insensitive Voltage Buffer 一种快速沉降温度不敏感电压缓冲器
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635340
Zhang Ya-cong, Chen Zhongjian, Lu Wengao, Gao Jun, Ji Lijiu, Zhao Baoying
{"title":"A Fast-settling Temperature-Insensitive Voltage Buffer","authors":"Zhang Ya-cong, Chen Zhongjian, Lu Wengao, Gao Jun, Ji Lijiu, Zhao Baoying","doi":"10.1109/EDSSC.2005.1635340","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635340","url":null,"abstract":"A fast-settling, temperature-insensitive voltage buffer is analyzed and designed. Class AB output stage in the buffer leads to high slew rate with relatively low power dissipation. The current switch not only sets the quiescent current of the output transistors, but also compensates the variation of Vth with temperature, which makes the buffer workable in a wide range of temperature. Simulation results show that the 0.1% settling time with 2V input step and 2OpF load is always less than 165ns when the temperature varies from 0°C to 100°C while the dissipation is less than 3mW. The die area without pads in 0.5um CMOS process is 350* 150um2.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125785329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Explicit Analytical Charge-Based Model of Asymmetrical Double Gate MOSFET 非对称双栅MOSFET显式解析电荷模型
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635255
M. Reyboz, O. Rozeau, T. Poiroux, P. Martín, G. Lecarval, J. Jomaah
{"title":"Explicit Analytical Charge-Based Model of Asymmetrical Double Gate MOSFET","authors":"M. Reyboz, O. Rozeau, T. Poiroux, P. Martín, G. Lecarval, J. Jomaah","doi":"10.1109/EDSSC.2005.1635255","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635255","url":null,"abstract":"This paper provides an explicit analytical charge-based model of Asymmetrical Double Gate (ADG) MOSFET. Its is based on Poisson equation resolution and field continuity equations, and gives explicit analytical expressions of the inversion charge and the drain current considering a long undoped transistor. There are no charge-sheet approximation and no fitting parameter. Consequently, this is a fully analytical and predictive model allowing to describe planar DG MOSFET as well as FinFET. The validity of this model is demonstrated by comparisons with Atlas simulations.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121927166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wide Tuning Range of A CMOS RF Bandpass Filter For Wireless Applications 用于无线应用的CMOS RF带通滤波器的宽调谐范围
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635204
Zhiqiang Gao, Mingyan Yu, Y. Ye, Jianguo Ma
{"title":"Wide Tuning Range of A CMOS RF Bandpass Filter For Wireless Applications","authors":"Zhiqiang Gao, Mingyan Yu, Y. Ye, Jianguo Ma","doi":"10.1109/EDSSC.2005.1635204","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635204","url":null,"abstract":"A 2ndorder RF bandpass filter with high-Q active inductor using low-voltage is presented. In the filter, a design technique for a tunable high-Q CMOS active inductor operating in the wide RF-band is described. Simulated performance is presented showing that the center frequency of filter using a 0.25-um CMOS process can be operated at the 1.60G∼2.45GHz frequency band under a 1.8V power supply and quality factor is adjusted from 30∼200 when fc≈2.45GHz.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121084388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation 采用浅沟槽隔离的NMOS和PMOS表面沟道晶体管的异常窄宽度效应
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635391
W. Lau, K. See, C. Eng, W. K. Awl, K. Jo, K. Tee, J.Y. Lee, E. Quek, H. Kim, S.T.H. Chan, L. Chan
{"title":"Anomalous Narrow Width Effect in NMOS and PMOS Surface Channel Transistors Using Shallow Trench Isolation","authors":"W. Lau, K. See, C. Eng, W. K. Awl, K. Jo, K. Tee, J.Y. Lee, E. Quek, H. Kim, S.T.H. Chan, L. Chan","doi":"10.1109/EDSSC.2005.1635391","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635391","url":null,"abstract":"NMOS surface-channel transistors using shallow trench isolation (STI) is known to show reverse narrow width effect (RNWE) such that the threshold voltage becomes smaller when the channel width decreases. We found that by using a phosphorus deep S/D implant in addition to an arsenic deep S/D implant, the threshold voltage first becomes larger when the channel width decreases and then later becomes smaller when the channel width further decreases for NMOS transistors with very small gate lengths. We attribute such an anomalous narrow width effect to an enhancement of TED due to Si interstitials generated by the phosphorus implant. PMOS transistors show up a much stronger anomalous narrow width effect compared to NMOS transistors. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic TED due to Si interstitials generated by the deep boron S/D implant.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125675186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Formation of very fine pit and dot arrays using EB writing for ultrahigh density storage toward 1 Tb/in2 使用EB写入形成非常精细的坑和点阵列，用于达到1tb /in2的超高密度存储
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635277
S. Hosaka, H. Sano, A. Miyachi, K. Itoh, H. Sone
{"title":"Formation of very fine pit and dot arrays using EB writing for ultrahigh density storage toward 1 Tb/in2","authors":"S. Hosaka, H. Sano, A. Miyachi, K. Itoh, H. Sone","doi":"10.1109/EDSSC.2005.1635277","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635277","url":null,"abstract":"Fabrication of ultrahigh packed pit and dot arrays have been studied using conventional electron beam (EB) writing, and positive and negative EB resists, ZEP520 and calixarene, respectively. Using fine electron beam with high probe current and very thinner resists, we demonstrate that the negative resist has a potential to achieve an ultrahigh density storage with both bit pitch (BP) and track pitch (TP) of <30 nm and a dot diameter of <15 nm, although the positive resist has a limitation at a BP of 60nm and a TP of 40nm. This dot array opens a way toward >1 trillion bits per inch2(Tb/in2) storage technology.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133531789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Two dimensional phase sensitive surface plasmon resonance biosensor array using microfluidic flow circuit platform 基于微流控电路平台的二维相敏表面等离子体共振生物传感器阵列
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635374
Chi Lok Wong, H. Ho, K. Lei, W. Li, K. Chan, W. Law, Shu-yuen Wu, S. Kong, Chinlon Lin
{"title":"Two dimensional phase sensitive surface plasmon resonance biosensor array using microfluidic flow circuit platform","authors":"Chi Lok Wong, H. Ho, K. Lei, W. Li, K. Chan, W. Law, Shu-yuen Wu, S. Kong, Chinlon Lin","doi":"10.1109/EDSSC.2005.1635374","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635374","url":null,"abstract":"The integration between 2D SPR differential phase imaging sensor and microfluidic flow circuit is presented. It provides the advantages of high throughput, high sensitivity and label free detection to meet the present needs in biomechnical market. The differential phase scheme between p- and s- polarization enable elimination of all common-path phase noise while keeping the phase change caused by SPR effect. System sensitivity of the detection sensitivity of our setup is 0.44μg /ml is obtained for salt / water mixture sensing. BSA antigen and antibody binding reaction detection is further demonstrated. The system shows the capability of simultaneous detection for both specific and non-specific binding reactions in a micro-chamber array.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"755 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modifications for Reliability of Bootstrapped Switches in Low Voltage Switched-Capacitor Circuits 低压开关电容电路中自举开关可靠性的改进
2005 IEEE Conference on Electron Devices and Solid-State Circuits Pub Date : 2005-12-19 DOI: 10.1109/EDSSC.2005.1635304
Shun Yao, Xiaobo Wu, Xiaolang Yan
{"title":"Modifications for Reliability of Bootstrapped Switches in Low Voltage Switched-Capacitor Circuits","authors":"Shun Yao, Xiaobo Wu, Xiaolang Yan","doi":"10.1109/EDSSC.2005.1635304","DOIUrl":"https://doi.org/10.1109/EDSSC.2005.1635304","url":null,"abstract":"One of the possible solutions to the low voltage applications of modern integrated circuit, which was widely demanded by recently developed submicron CMOS technology, is the bootstrapped switch technique. In order to overcome its drawbacks such like the reliability issue on the main signal switch during the clock transition, three different approaches were proposed in this paper along with the simulation results. The oxide lifetime can benefit from these modifications without much circuit degradation.","PeriodicalId":429314,"journal":{"name":"2005 IEEE Conference on Electron Devices and Solid-State Circuits","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128299167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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