Integration Design of Chip and Package for Cost-Effective High-Speed Applications

Abstract

Low cost is the trend for consumer electronics. However, the challenges of the LCD-TV processor using cost-effective two-layer ball grid array (BGA) packages suffer from serious crosstalk and return loss due to lack of a solid plane to suppress the coupling effect and control the trace impedance. Two types of two-layer BGA packages were measured and simulated using a 3D full-wave electromagnetic field solver and an EM-based 3D parasitic extractor to analyze their speed limitations and power coupling between the signals and the power net. The results indicated the signal coupling is the dominant factor for insertion loss. Thus, the design guidelines and specifications using two-layer BGA packages are proposed for development of the next generation processors.