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The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.最新文献

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Low-error carry-free fixed-width multipliers and their application to DCT/IDCT 低误差无载波定宽乘法器及其在DCT/IDCT中的应用
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412795
Tso-Bing Juang, Shen-Fu Hsiao, Shiann-Rong Kuang, Ming-Yu Tsai
{"title":"Low-error carry-free fixed-width multipliers and their application to DCT/IDCT","authors":"Tso-Bing Juang, Shen-Fu Hsiao, Shiann-Rong Kuang, Ming-Yu Tsai","doi":"10.1109/APCCAS.2004.1412795","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412795","url":null,"abstract":"In this paper, we propose a low-error fixed-width redundant multiplier design. The design is based on the statistical analysis of the value of the truncated partial products in binary signed-digit representation with modified Booth encoding. The overall truncation error is significantly reduced with negligible hardware overhead. Simulation on DCT/IDCT of images with 256 gray levels shows our proposed multiplication design has higher PSNR/SNR.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124982095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of novel hybrid techniques for short-term unit commitment problem 新型混合技术在机组短期承诺问题中的应用
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413093
Gwo-Ching Liao
{"title":"Application of novel hybrid techniques for short-term unit commitment problem","authors":"Gwo-Ching Liao","doi":"10.1109/APCCAS.2004.1413093","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413093","url":null,"abstract":"This paper presents a Hybrid Genetic Algorithm(GA) and Simulated Annealing (SA) method (GA-SA) for solving short-term thermal generating Unit Commitment (UC) problems. The UC problem involves determining the start-up and shutdown schedules for generating units to meet the forecasted demand at the minimum cost. The commitment schedule must satisfy other constraints such as the generating limits per unit, reserve and individual units.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"51 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114045878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An optimization approach for SoC FSM verification SoC FSM验证的优化方法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412822
Wang Zhonghai, Wan Jinxiang, Ye Yi-zheng
{"title":"An optimization approach for SoC FSM verification","authors":"Wang Zhonghai, Wan Jinxiang, Ye Yi-zheng","doi":"10.1109/APCCAS.2004.1412822","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412822","url":null,"abstract":"Verification is a bottleneck in IC design, and how to do FSM verification is the main part of the problem. A new approach based on digraph theory and mathematical programming, whose target is to verify all the state transitions in the optimized time, is presented in This work. The FSM verification path can be generated automatically by this approach and this method has been applied in the C*SOC verification environment, and the experimental result shows the method can accelerate the verification process efficiently.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122643918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
System optimization of contents delivery network with information-zooming function 具有信息缩放功能的内容传递网络系统优化
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412801
K. Takada, H. Watanabe
{"title":"System optimization of contents delivery network with information-zooming function","authors":"K. Takada, H. Watanabe","doi":"10.1109/APCCAS.2004.1412801","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412801","url":null,"abstract":"This paper proposed a new CDN with information zooming function, which delivers generic/specific contents by mirror servers and customizing servers. First, algorithms for the optimum location problem of p mirror servers and q customizing servers are presented. The system optimization problem of Z-CDN is investigated, and effective algorithms for optimum number and location of mirror/customizing servers with the minimum system cost are presented. Proposed Z-CDN may satisfy varieties of individual demands","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127683080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quantum circuit design of 8x8 discrete fourier transform using its fast computation flow graph 利用其快速计算流程图设计8x8离散傅立叶变换的量子电路
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413000
C. Tseng, T. Hwang
{"title":"Quantum circuit design of 8x8 discrete fourier transform using its fast computation flow graph","authors":"C. Tseng, T. Hwang","doi":"10.1109/APCCAS.2004.1413000","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413000","url":null,"abstract":"In this paper, quantum circuit design of 8x8 discrete cosine transform (DCT) is investigated. The proposed design procedure can be divided into the following three steps. First, the DCT matrix is decomposed into the product of sparse matrices based on its fast computation flow graph. Second, each sparse matrix is implemented by elementary quantum gates. Third, cascade the circuits of sparse matrices to obtain the final circuit. The proposed method makes fast DCT computation algorithm in digital signal processing be suitable for implementation in quantum computer.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"889 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131985698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Linearly independent helix transforms over GF(3) 线性无关螺旋在GF(3)上的变换
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413030
Cheng Fu, B. Falkowski
{"title":"Linearly independent helix transforms over GF(3)","authors":"Cheng Fu, B. Falkowski","doi":"10.1109/APCCAS.2004.1413030","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413030","url":null,"abstract":"New classes of linearly independent ternary transforms over Galois Field (3) called linearly independent helix transforms are introduced here. Four types of such helix transform matrices with detailed recursive equations are described. Various properties of helix transform matrices, their mutual relations and special cases for selected temary logic hnctions as well as their butterfly diagrams and computational costs are also discussed. Experimental results comparing four new helix transforms with ternary Reed-Muller transforms are also discussed.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134422387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic protocol translation and template based interface synthesis for IP reuse in SoC SoC中IP复用的自动协议转换和基于模板的接口合成
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412825
Y. Hwang, Sung-Chun Lin
{"title":"Automatic protocol translation and template based interface synthesis for IP reuse in SoC","authors":"Y. Hwang, Sung-Chun Lin","doi":"10.1109/APCCAS.2004.1412825","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412825","url":null,"abstract":"Reuse of intellectual property (IP) is crucial in SoC design. The discrepancies in interface logic and communication/bus protocols among IPs, however, remain as the main obstacle in system integration. We examine the interface logic generation problem and propose a novel scheme to automate the process. The scheme consists of an automatic communication/bus protocol translation and a template based interface logic/bus wrapper generation. Real case test bench, e.g. AHB in AMBA v.s. BVCI in VCI was applied to verify the correctness and the efficiency of the generated interface. The design is also implemented in FPGA and incurred interface circuitry overhead is small.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134604113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Real-time 3D image computation using LUT-based DSP systems 基于lut的DSP系统的实时三维图像计算
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412772
H. Khali, M. Riyadh, A. Araar
{"title":"Real-time 3D image computation using LUT-based DSP systems","authors":"H. Khali, M. Riyadh, A. Araar","doi":"10.1109/APCCAS.2004.1412772","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412772","url":null,"abstract":"In a typical embedded laser-based acquisition system, real-time 3D image computation may be affected by several main factors, like processor speed, complexity of re-mapping functions, the size of the 3D image and the correctness of optical data (artifact correction). To achieve the desired performance, the designer may choose a fully hardware-based solution. However, this will increase the system cost. In this paper, we propose a hardware-software system design framework based on a DSP processor, and look-up tables (LUT) to compute a 3D image in real-time and achieve the desired throughput","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115682790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improved K nearest neighbor classification algorithm 改进的K近邻分类算法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413076
Yu-Long Qiao, Jeng-Shyang Pan, Shenghe Sun
{"title":"Improved K nearest neighbor classification algorithm","authors":"Yu-Long Qiao, Jeng-Shyang Pan, Shenghe Sun","doi":"10.1109/APCCAS.2004.1413076","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413076","url":null,"abstract":"A novel and efficient algorithm is proposed to reduce the computational complexity for KNN classification. It uses two important features, the approximation coefficient of a fully decomposed feature vector with Haar wavelet and the variance of the corresponding untransformed vector, to produce two efficient test conditions. Since those vectors that are impossible to be the k closest vectors in the design set are kicked out quickly by these conditions, this algorithm saves largely the classification time and have the same classification performance as that of the exhaustive search classification algorithm. Experimental results based on texture image classification verify our proposed algorithm.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117093987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A new variable step size method for the LMS adaptive filter 一种新的变步长LMS自适应滤波方法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412808
J. Sanubari
{"title":"A new variable step size method for the LMS adaptive filter","authors":"J. Sanubari","doi":"10.1109/APCCAS.2004.1412808","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412808","url":null,"abstract":"In this paper, a new cost function for improving the performance of the least mean square (LMS) method is proposed. The proposed cost function is convex. The first derivative of the proposed cost function is continued. The proof of the convexity of the function is presented. The theoretical study of the convergence characteristic shows that lower error and faster convergence can be obtained by using the proposed function. The proposed function provide large weighting factor when the error is small. On the hand, when the error is large, a small weighting factor is applied. By doing so, the effect of the noise can be reduced. The simulation results show that indeed we can lower final error and faster convergence when small alpha is applied","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"10886 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117281778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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