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The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.最新文献

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Design and application of variable fractional order differentiator 可变分数阶微分器的设计与应用
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412781
C. Tseng
{"title":"Design and application of variable fractional order differentiator","authors":"C. Tseng","doi":"10.1109/APCCAS.2004.1412781","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412781","url":null,"abstract":"In this paper, the design problem and application of the variable fractional order differentiator (VFOD) are investigated. First, the Cauchy integral formula is generalized to define the fractional derivative of function. Then, the weighted least squares method is presented to design FIR variable fractional order differentiator. Finally, VFOD is applied to synthesize and analyze 1/f noise process. Simulation results demonstrate that the proposed method can generate more accurate 1/f noise than the conventional fractional differencing method","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116108324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Ear-type systems Ear-type系统
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412670
R. Newcomb
{"title":"Ear-type systems","authors":"R. Newcomb","doi":"10.1109/APCCAS.2004.1412670","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412670","url":null,"abstract":"Ear-Type Systems are ones which mimic the behavior of the biological ear via electronic systems and circuit theory. The physiological structure of the ear leading to the architecture under investigation will be reviewed. From that a circuit theory based upon transfer scattering in four port structures will be introduced. Using stimulated emissions of the ear, the parameters of these structures are obtained and kom them various investigations proceed. For example one can locate damage to the inner ear and by taking inverses of the located sections in some cases the damage can be cancelled out. In other cases possible neural stimulation of the inner ear leading to ringing in the ear may be determined. Various circuits, such as switched current ones, to realize the transfer scattering matrices will be discussed.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123065255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Packet analyzer for JPEG2000 codestreams and its VHDL model JPEG2000码流包分析器及其VHDL模型
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413026
M. Kurosaki, A. Ikeda, K. Munadi, H. Kiya
{"title":"Packet analyzer for JPEG2000 codestreams and its VHDL model","authors":"M. Kurosaki, A. Ikeda, K. Munadi, H. Kiya","doi":"10.1109/APCCAS.2004.1413026","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413026","url":null,"abstract":"In this paper, a packet analyzer for JPEG2000 codestreams is designed and its switching power and cell areas are estimated. This analyzer is intended to treat packets in the PEG2000 codestream, where the packet header and body data are separated from each other for further processing, such as encryption, partial scrambling, data hiding, and error correction. This VHDL-modeled analyzer can work at a bit rate of 50 Mb/s at minimum cost. Thus, it is suitable for real-time applications.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new method for short term electric load forecasting 电力负荷短期预测的一种新方法
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413092
Gwo-Ching Liao
{"title":"A new method for short term electric load forecasting","authors":"Gwo-Ching Liao","doi":"10.1109/APCCAS.2004.1413092","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413092","url":null,"abstract":"An integrated genetic algorithm (GA)/tabu search (TS) and neural fuzzy network (NFN) method for load forecasting is presented In this work. A neural fuzzy network (NFN) was used for the initial load forecasting. Then we used CGA and TS to find the optimal solution of the parameters of the NFN, instead of back-propagation (BP). First the GA generates a set of feasible solution parameters and then puts the solution into the TS. We combined both methods to try and obtain both advantages, and in doing so eliminate the drawback of the traditional ANN training by BP.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121870660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel predict hexagon search algorithm for fast block motion estimation on H.264 video coding 一种新的预测六边形搜索算法用于H.264视频编码中的快速块运动估计
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412836
T. Tsai, Yu-Nan Pan
{"title":"A novel predict hexagon search algorithm for fast block motion estimation on H.264 video coding","authors":"T. Tsai, Yu-Nan Pan","doi":"10.1109/APCCAS.2004.1412836","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412836","url":null,"abstract":"The upcoming video coding standard, MPEG-4 AVC/JVT/H.264, motion estimation is allowed to use multiple references and multiple block sizes to improve the rate-distortion performance. However, full exhaustive search of all block sizes is computational intensive with complexity increasing linearly to the number of allowed reference frame and block size. A novel search algorithm, predict hexagon search (PHS), is proposed. The PHS pattern is applied by the comparison with the hexagon based search pattern. It can predict the hexagon search pattern in horizontal or vertical direction. Analysis shows that the speed improvement of the PHS over the diamond search (DS) and the hexagon based search (HEXBS) is about 58% and 53% respectively.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":" 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113948207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Booth memoryless modular multiplier with signed-digit number representation 布斯无记忆模乘法器，有符号数字表示
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412681
Shuangching Chen, Shugang Wei, K. Shimizu
{"title":"Booth memoryless modular multiplier with signed-digit number representation","authors":"Shuangching Chen, Shugang Wei, K. Shimizu","doi":"10.1109/APCCAS.2004.1412681","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412681","url":null,"abstract":"We present new Booth modular multipliers with a signed-digit number representation. The proposed Booth algorithm can recode the multiplier in which every two-digit has an element of the set {-2, -1, 0, 1, 2}. In a serial modular multiplier, the proposed Booth modular multipliers compared to earlier ones offer savings up 50 percent in the execution time. In a parallel multiplier, it can be up to 18.76 percent in the implementation area for modulus m = 255.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121079407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic load balancing for wired and wireless internet access 有线和无线互联网接入的动态负载平衡
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413022
L. Chang, C.F. Tai, D. Wang, K. Lai
{"title":"Dynamic load balancing for wired and wireless internet access","authors":"L. Chang, C.F. Tai, D. Wang, K. Lai","doi":"10.1109/APCCAS.2004.1413022","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413022","url":null,"abstract":"In this paper we propose a new algorithm, which analyzes arrival rate and link rate (or service rate) to fmd the weight for each of the outbound links automatically. Our purpose is to distribute traffic load evenly to each of the links. We also discuss the outbound links with wireless connections. The impact of retransmitting packets due to the high error probability on the traffic load will be considered in our system. The simulation results show that the proposed algorithm improves the performance for about ten to seventeen percentages.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122490498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
High-speed logic circuitry used bootstrapped technology and low-temperature poly-silicon technology for TFT-LCD panel TFT-LCD面板的高速逻辑电路采用自启动技术和低温多晶硅技术
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413050
K. Matsunaga, Y. Suzuki, K. Umeda
{"title":"High-speed logic circuitry used bootstrapped technology and low-temperature poly-silicon technology for TFT-LCD panel","authors":"K. Matsunaga, Y. Suzuki, K. Umeda","doi":"10.1109/APCCAS.2004.1413050","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413050","url":null,"abstract":"In this paper, a high-speed logic circuitry used bootstrapped technology and Low Temperature Poly Silicon (LTPS) technology for TFT- LCD panel is proposed. The high-speed logic circuitry realizes the high-speed operation due to applying the wider swing-voltage than the power-supply voltage by using the bootstrapped technology. As the results, the new logic circuitry can operate at the operational frequency by around 10 times than the conventional circuitry under the conditions of 0.5pF load-capacitor and +1OV power-supply voltages.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122685602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Determination of bandwidth and free spectral range for the silicon based ring resonators and racetrack microcavity resonators 硅基环形谐振器和赛道微腔谐振器的带宽和自由光谱范围的测定
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1412806
S. Khuntaweetep, S. Somkuarnpanit, K. Sae-tang
{"title":"Determination of bandwidth and free spectral range for the silicon based ring resonators and racetrack microcavity resonators","authors":"S. Khuntaweetep, S. Somkuarnpanit, K. Sae-tang","doi":"10.1109/APCCAS.2004.1412806","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1412806","url":null,"abstract":"This paper determines the free spectral range, FSR, and the half-power bandwidth, HPBW, of the racetrack microresonator, RTM, against the ring microresonator, RM, on silicon substrate. The accurate numerical FDTD has been used to calculate its characteristics in optical communication wavelengths. At the optimum size of the device, the spectral response is calculated, which leads to two relationships between HPBW against the coupling efficiency and FSR against the racetrack round trip. These relationships can be used to determine the possibly maximum FSR and the least HPBW for the RM. Both parameters are degraded for the high coupling RTM","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126412102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders (RAMAO) 基于自适应阶数的合理Arnoldi方法的VLSI互连多点模型约简
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. Pub Date : 2004-12-06 DOI: 10.1109/APCCAS.2004.1413052
Herng-Jer Lee, C. Chu, W. Feng
{"title":"Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders (RAMAO)","authors":"Herng-Jer Lee, C. Chu, W. Feng","doi":"10.1109/APCCAS.2004.1413052","DOIUrl":"https://doi.org/10.1109/APCCAS.2004.1413052","url":null,"abstract":"This work proposes the rational Arnoldi method with adaptive orders for high-speed VLSI interconnect reductions. It is based on an extension of the classical multi-point Pade approximation by using the rational Arnoldi iteration approach. Given a set of expansion points, the transfer function error at each expansion point is derived first. In each iteration of the proposed algorithm, the expansion frequency corresponding to the maximum output moment error is chosen. The corresponding reduced-order model yields the greatest output moment improvement.","PeriodicalId":426683,"journal":{"name":"The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129398115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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