2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献

{"title":"Power consumption characterization, modeling and estimation of electric vehicles","authors":"N. Chang, Donkyu Baek, Jeongmin Hong","doi":"10.1109/ICCAD.2014.7001349","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001349","url":null,"abstract":"Rapid electric vehicle (EV) penetration gives a threatening challenge in electric energy generation. An 1,814 kg curb weight full electric vehicle driving 18,129 km/year consumes electricity energy equivalent to 74% of the total residential electricity use per person in the US. This implies that 27% more nationwide electricity generation is needed when 70% of passenger vehicles are replaced with EVs. This paper is the first step toward systematic EV design-time and runtime optimization. We introduce instantaneous power consumption modeling of an EV by the curb weights, speed, acceleration, road slope, passenger and cargo weights, motor capacity, and so on, as a battery discharge model. The model also considers the onboard charger, regenerative braking and so on, as a battery charge model. To insure model fidelity, we fabricate a lightweight custom EV, perform extensive measurement, and derive model coefficients using multivariable regression analysis. We estimate the EV instantaneous power consumption of a given speed and route profiles and verify the estimation fidelity with a real test run data.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121120246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards a standard flow for system level power modeling","authors":"N. Dhanwada, W. R. Davis, J. Frenkil","doi":"10.1109/ICCAD.2014.7001333","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001333","url":null,"abstract":"Power efficiency is a key design objective for most SoCs today and designers continue to search for new approaches to low power design. As transistor level, gate level and RTL methods have become well understood and widely adopted, interest has grown in power aware system design. This interest has arisen along with the overall growth and adoption of SystemC for functional modeling and simulation. In a comprehensive power aware flow, power analyses and optimizations occur during all three major design phases: System Design, RTL Design, and Implementation. These activities require models that represent the power characteristics of each design element. However, unlike RTL Design and Implementation, System Design has no standard power modeling or analysis mechanisms. This lack of abstract, system level power models inhibits system level power analysis: where models are unavailable the flow is unrealized, where models are available the accuracy and flexibility is often limited. This issue motivated the development of modeling capabilities for IP block abstract power models for use in all phases of SoC design. This development built upon existing gate level modeling semantics and flows. This presentation will begin with an overview of existing gate level power modeling capabilities, using the Liberty modeling language as the example. The interpretation of the models by power calculation applications will be described, including the interaction between power models and simulation data. Requirements beyond the existing gate level capabilities will be described. Key requirements include black-box and grey-box modeling styles, methods for handling the exponential explosion of power states and power state transitions, automatic model generation, power component categorization, and descriptions of power structure and power operation. Some of these requirements have already been implemented while others are in the proposal stage. Example usage of such a system level model will be illustrated with a Transaction Level (TLM) Simulation. The example will illustrate how the model is used to produce dynamic and leakage power calculations from the TLM simulation data.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121243541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Functional modeling compiler for system-level design of automotive cyber-physical systems","authors":"A. Canedo, Jiang Wan, M. A. Faruque","doi":"10.1109/ICCAD.2014.7001327","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001327","url":null,"abstract":"A novel design methodology, associated algorithms, and tools for the design of complex automotive cyber-physical systems are presented. Rather than supporting the critical path where most resources are spent, we preemptively target the concept design phase that determines 75% of a vehicle's cost. In our methodology, the marriage of systems engineering principles with high-level synthesis techniques results in a Functional Modeling Compiler capable of generating high-fidelity simulation models for the design space exploration and validation of multiple cyber-physical (ECUs+Physics) vehicle architectures. Using real-world automotive use-cases, we demonstrate how functional models capturing cyber-physical aspects are synthesized into high-fidelity simulation models.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126926017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Logic synthesis and a generalized notation for memristor-realized material implication gates","authors":"Anika Raghuvanshi, M. Perkowski","doi":"10.1109/ICCAD.2014.7001393","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001393","url":null,"abstract":"The paper presents new logic synthesis methods for single-output incomplete multi-level binary circuits using Memristor-based material implication gates. The first method follows Lehtonen's assumption of using only two working memristors. The algorithm minimizes the number of implication (IMPLY) gates, which corresponds to minimizing the number of pulses or the delay time. This greedy search method uses essential and secondary essential primes, does not require solving the covering problem, is fast, and produces high quality results. We compare it to other synthesis methods, such as the modified SOP and Exclusive-Or Sum of Products (ESOP) with minimum number of working memristors. We analyze the problem of reduction in IMPLY gate count by adding more working memristors and introduce Imply Sequence Diagrams, a new notation, similar to one used in reversible logic.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116264367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MPME-DP: Multi-population moment estimation via dirichlet process for efficient validation of analog/mixed-signal circuits","authors":"M. Zaheer, Xin Li, Chenjie Gu","doi":"10.1109/ICCAD.2014.7001369","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001369","url":null,"abstract":"Moment estimation is one of the most important tasks to appropriately characterize the performance variability of today's nanoscale integrated circuits. In this paper, we propose an efficient algorithm of multi-population moment estimation via Dirichlet Process (MPME-DP) for validation of analog and mixed-signal circuits with extremely small sample size. The key idea is to partition all populations (e.g., different environmental conditions, setup configurations, etc.) into groups. The populations within the same group are similar and their common knowledge can be extracted to improve the accuracy of moment estimation. As will be demonstrated by the silicon measurement data of a high-speed I/O link, MPME-DP reduces the moment estimation error by up to 65% compared to other conventional estimators.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133584051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A systematic approach for analyzing and optimizing cell-internal signal electromigration","authors":"G. Posser, Vivek Mishra, Palkesh Jain, R. Reis, S. Sapatnekar","doi":"10.1109/ICCAD.2014.7001395","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001395","url":null,"abstract":"Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects, and is used to analyze the lifetime of large benchmark circuits. Further, a method for optimizing the circuit lifetime using minor layout modifications is proposed.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"35 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132275415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy-efficient architecture for advanced video memory","authors":"F. Sampaio, M. Shafique, B. Zatt, S. Bampi, J. Henkel","doi":"10.1109/ICCAD.2014.7001343","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001343","url":null,"abstract":"An energy-efficient hybrid on-chip video memory architecture (enHyV) is presented that combines private and shared memories using a hybrid design (i.e., SRAM and emerging STT-RAM). The key is to leverage the application-specific properties to efficiently design and manage the enHyV. To increase STT-RAM lifetime, we propose a data management technique that alleviates the bit-toggling write occurrences. An adaptive power management is also proposed for static-energy savings. Experimental results illustrate that enHyV reduces on-chip static memory energy compared to SRAM-only version of enHyV and to state-of-art AMBER hybrid video memory [9] by 66%-75% and 55%-76%, respectively. Furthermore, negligible external memory energy consumption is required for reference frames communication (98% lower than state-of-the-art Level C+ technique [18]). Our data management significantly improves the enHyV STT-RAM lifetime, achieving 0.83 of normalized lifetime (near to the optimal case). Our hybrid memory design and management incur low overhead in terms of latency and dynamic energy.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128842615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TonyChopper: A desynchronization package","authors":"Zhao Wang, Xiao He, C. Sechen","doi":"10.1109/ICCAD.2014.7001390","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001390","url":null,"abstract":"TonyChopper is an integrated set of tools for digital circuit desynchronization. The core portion of TonyChopper is a tool that reads a gate-level synthesized synchronous digital circuit and transforms it to an asynchronous circuit by implementing a novel desynchronization approach. Pre-layout and post-layout verification tools are also provided in this package. The proposed new asynchronous design method is compatible with conventional synthesis, placement and routing (PnR) and other computer-aided design (CAD) tools. Only a conventional standard cell library is used. Compared to traditional synchronous static CMOS design, the proposed design is highly suitable for very low voltage operation. An auto-sleep strategy is also integrated in the tool for minimizing the leakage power for circuits. Different benchmark circuits were implemented in IBM 130nm technology to show that the design approach used in TonyChopper is highly robust even in the sub-threshold regime. The layout for every benchmark circuit was generated using a Cadence PnR tool. Hspice simulation for both the synchronous benchmark circuit and the desynchronized version provided comparison of the delay, area and leakage power for each benchmark circuit. Monte Carlo simulations were performed for each benchmark circuit to demonstrate high robustness and delay insensitivity for near threshold supply voltages with substantial threshold voltage (VT) variations.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115013254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Vulnerability assessment and defense technology for smart home cybersecurity considering pricing cyberattacks","authors":"Yang Liu, Shiyan Hu, Tsung-Yi Ho","doi":"10.1109/ICCAD.2014.7001350","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001350","url":null,"abstract":"Smart home, which controls the end use of the power grid, has become a critical component in the smart grid infrastructure. In a smart home system, the advanced metering infrastructure (AMI) is used to connect smart meters with the power system and the communication system of a smart grid. The electricity pricing information is transmitted from the utility to the local community, and then broadcast through wired or wireless networks to each smart meter within AMI. In this work, the vulnerability of the above process is assessed. Two closely related pricing cyberattacks which manipulate the guideline electricity prices received at smart meters are considered and they aim at reducing the expense of the cyberattacker and increasing the peak energy usage in the local community. A countermeasure technique which uses support vector regression and impact difference for detecting anomaly pricing is then proposed. These pricing cyberattacks explore the interdependance between the transmitted electricity pricing in the communication system and the energy load in the power system, which are the first such cyber-attacks in the smart home context. Our simulation results demonstrate that the pricing cyberattack can reduce the attacker's bill by 34.3% at the cost of the increase of others' bill by 7.9% on average. In addition, the pricing cyberattack can unbalance the energy load of the local power system as it increases the peak to average ratio by 35.7%. Furthermore, our simulation results show that the proposed countermeasure technique can effectively detect the electricity pricing manipulation.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124016516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing","authors":"Ping Chi, Cong Xu, Zhang Tao, Xiangyu Dong, Yuan Xie","doi":"10.1109/ICCAD.2014.7001367","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001367","url":null,"abstract":"High reliability, availability, and serviceability are critical for modern large-scale computing systems. As an effective error recovery mechanism, checkpointing has been widely used in such systems for their survival from unexpected failures. The conventional checkpointing schemes, however, are time-consuming due to the limited I/O bandwidth between the DRAM-based main memory and the backup storage. To mitigate the checkpoint overhead, we propose a fast local checkpointing scheme by leveraging Multi-Level Cell (MLC) STT-RAM. We take advantage of the unique features of MLC STT-RAM to accelerate local checkpointing. Our experimental results show that the average performance overhead is less than 1% in a multi-programmed four-core process node with a 1-second local checkpoint interval. The evaluation results also demonstrate that using MLC STT-RAM is an energy-efficient solution.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125952262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}