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2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献

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iTimerC: Common path pessimism removal using effective reduction methods iTimerC:使用有效的减少方法消除常见路径悲观情绪
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001414
Yu-Ming Yang, Yu-Wei Chang, I. Jiang
{"title":"iTimerC: Common path pessimism removal using effective reduction methods","authors":"Yu-Ming Yang, Yu-Wei Chang, I. Jiang","doi":"10.1109/ICCAD.2014.7001414","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001414","url":null,"abstract":"Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis. To avoid exhaustive exploration on all paths in a design, in this paper, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, and dynamic bounding. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127351546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
More effective power-gated circuit optimization with multi-bit retention registers 更有效的功率门控电路优化与多位保持寄存器
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001354
Shu-Hung Lin, Mark Po-Hung Lin
{"title":"More effective power-gated circuit optimization with multi-bit retention registers","authors":"Shu-Hung Lin, Mark Po-Hung Lin","doi":"10.1109/ICCAD.2014.7001354","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001354","url":null,"abstract":"Applying retention registers is one of the most effective and efficient approaches to keep flip-flop states in power-gated circuits during the sleep mode. Instead of replacing each flip-flop in a power-gated circuit with a single-bit retention register (SBRR), recent research has shown that applying multi-bit retention registers (MBRRs) can effectively reduce the storage size, and hence save more chip area and leakage power. However, the previous work simply adopted greedy heuristics for power-gated circuit optimization with MBRRs, which first break feedback paths and then iteratively replace a flip-flop covering the maximum number of (k-1)-link paths with a k-bit retention register. Different from the previous work, this paper presents an even more effective approach based on integer-linear-programming (ILP) formulation with simultaneous consideration of all feedback paths. Experimental results show that the proposed approach can further reduce up to 46% storage size compared with the previous work.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130379393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A unifying and robust method for efficient envelope-following simulation of PWM/PFM DC-DC converters 一种统一鲁棒的PWM/PFM DC-DC变换器高效包络跟踪仿真方法
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001417
Ya Wang, Peng Li, Suming Lai
{"title":"A unifying and robust method for efficient envelope-following simulation of PWM/PFM DC-DC converters","authors":"Ya Wang, Peng Li, Suming Lai","doi":"10.1109/ICCAD.2014.7001417","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001417","url":null,"abstract":"The envelope-following (EF) simulation of practical DC-DC converters is challenging due to the presence of digital behavior, strong nonlinearity, complex frequency module schemes and feedback loops. This paper presents a novel EF method for time-domain analysis of DC-DC converters based upon a numerically robust time-delayed phase condition to track the envelopes oaf circuit states under a varying switching frequency. We further develop an EF technique that is applicable to both fixed and varying switching frequency operations, thereby providing a unifying solution to converters with pulse-width modulation (PWM) and/or pulse-frequency modulation (PFM). The robustness and efficiency of the proposed method are demonstrated using several DC-DC converter and oscillator circuits modeled using the industrial standard BSIM4 transistor models. A significant runtime speedup of 30× with respect to the conventional transient analysis is achieved for PFM DC-DC converters with strong nonlinear switching characteristics.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
TKtimer: Fast & accurate clock network pessimism removal TKtimer:快速准确的时钟网络悲观情绪消除
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001415
Christos Kalonakis, Charalampos Antoniadis, Panagiotis Giannakou, Dimos Dioudis, G. Pinitas, G. Stamoulis
{"title":"TKtimer: Fast & accurate clock network pessimism removal","authors":"Christos Kalonakis, Charalampos Antoniadis, Panagiotis Giannakou, Dimos Dioudis, G. Pinitas, G. Stamoulis","doi":"10.1109/ICCAD.2014.7001415","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001415","url":null,"abstract":"As integrated circuit process technology progresses into the deep sub-micron region, the phenomenon of process variation has a growing impact on the design and analysis of digital circuits and more specifically in the accuracy and integrity of timing analysis methods. The assumptions made by the analytical models, impose excessive and unwanted pessimism in timing analysis. Thus, the necessity of removing the inherited pessimism is of utmost importance in favour of accuracy. In this paper an approach to the common path pessimism removal timing analysis problem, TKtimer, is presented. By utilizing certain key techniques such as branch-and-bound, caching, tasklevel parallelism and enhanced algorithmic techniques, the approach described by this paper is able to handle any type and size of clock network trees and showed 100% accuracy combined with reasonable execution time within a straightforward solution context.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126229479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite ICCAD-2014先进半导体节点和基准套件可制造性流程设计CAD竞赛
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001377
R. Topaloglu
{"title":"ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite","authors":"R. Topaloglu","doi":"10.1109/ICCAD.2014.7001377","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001377","url":null,"abstract":"We introduce the fill optimization problem and benchmarks. We provide two new hotspot definitions, slot line deviation and outliers, both of which pertain to yield. We provide the inputs, expected output, as well as objectives and constraints of the problem.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121121753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Application driven high level design in the era of heterogeneous computing 异构计算时代应用驱动的高层设计
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001331
R. Puri
{"title":"Application driven high level design in the era of heterogeneous computing","authors":"R. Puri","doi":"10.1109/ICCAD.2014.7001331","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001331","url":null,"abstract":"Summary form only given. Escalating costs of semiconductor technology and its lagging performance relative to historic trends is motivating acceleration and specialization as more impactful means to increase system value. Targeted specialization is being increasingly pursued as an important way to achieve dramatic improvements in workload acceleration. This requires a broad understanding of workloads, system structures, and algorithms to determine what to accelerate / specialize, and how, i.e., via SW?; via HW?; or via SW+HW? which presents many choices, necessitating co-optimization of SW and HW. In this talk, we will focus on an application driven approach to high level design for software and system co-optimization, based on inventing new software algorithms, that have strong affinity to hardware acceleration.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115279401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lifetime optimization for real-time embedded systems considering electromigration effects 考虑电迁移效应的实时嵌入式系统寿命优化
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001388
Taeyoung Kim, Bowen Zheng, Hai-Bao Chen, Qi Zhu, V. Sukharev, S. Tan
{"title":"Lifetime optimization for real-time embedded systems considering electromigration effects","authors":"Taeyoung Kim, Bowen Zheng, Hai-Bao Chen, Qi Zhu, V. Sukharev, S. Tan","doi":"10.1109/ICCAD.2014.7001388","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001388","url":null,"abstract":"In this article, we propose a new lifetime task optimization technique for real-time embedded processors considering the electromigration-induced reliability. The new approach is based on a recently proposed physics-based electromigration (EM) model for more accurate EM assessment of a power grid network at the chip level. We apply the dynamic voltage and frequency scaling (DVFS) (by selecting the performance states or p-states of the tasks to manage the power) and thus the lifetime of the processor running different tasks over their periods. We consider both single-rate and multi-rate embedded systems with preemption. To model the mean-time-to-failure (MTTF) of a task for a given p-state, response surface modeling is applied. We then frame the reliability optimization problem as the continuous constrained nonlinear optimization problem in which the system EM-induced reliability is maximized subject to the timing constraints, which is further solved by simulated annealing method. Experimental results show that for low utilization systems, significant reliability improvement can be achieved with even smaller power consumption than existing reliability-ignore scheduling method. The proposed method can lead to near Pareto's front trade-off between the power/energy and the lifetime compared to the existing task scheduling method.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115937782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
SuperPUF: Integrating heterogeneous Physically Unclonable Functions SuperPUF:整合异构物理不可克隆函数
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001391
Michael Wang, Andrew Yates, I. Markov
{"title":"SuperPUF: Integrating heterogeneous Physically Unclonable Functions","authors":"Michael Wang, Andrew Yates, I. Markov","doi":"10.1109/ICCAD.2014.7001391","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001391","url":null,"abstract":"Physically Unclonable Functions (PUFs) combat counterfeit ICs by identifying each chip using inherent process variation. PUFs must produce sufficiently many bits, but replicating the same PUF design requires care since process variation and its spatial correlation may change in the next 10 years. Additional challenges arise in system-on-chip and heterogeneous 3D integration of diverse PUFs. Responding to these challenges, we introduce methods for combining PUFs, with provisions for sampling process variation throughout the IC. When multiple sources of entropy are available, our optimization algorithms select sources to maximize joint entropy and minimize physical overhead. Empirical validation uses SPICE simulations for a 45nm technology node.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Fast path-based timing analysis for CPPR 基于路径的CPPR快速时序分析
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.5555/2691365.2691487
Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
{"title":"Fast path-based timing analysis for CPPR","authors":"Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong","doi":"10.5555/2691365.2691487","DOIUrl":"https://doi.org/10.5555/2691365.2691487","url":null,"abstract":"Common-path-pessimism removal (CPPR) is a pivotal step to achieve accurate timing signoff. Unnecessary pessimism might arise quality-of-result (QoR) concerns such as reporting worse violations than the true timing properties owned by the physical circuit. In other words, signoff timing report will conclude a lower clock frequency at which circuits can operate than actual silicon implementations. Therefore, we introduce in this paper a fast path-based timing analysis for CPPR. Unlike existing approaches which are dominated by explicit path search, we perform implicit path representation which yields significantly smaller search space and faster runtime. Specifically, our algorithm is superior in both space and time saving, from which the memory storage and important timing quantities are available in constant space and constant time per path during the search. Experimental results on industrial benchmarks released from TAU 2014 timing analysis contest have shown that our algorithm won the first place and achieved the best result in terms of accuracy and runtime over all participating teams.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121822880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Exact routing for digital microfluidic biochips with temporary blockages 精确路由的数字微流控生物芯片与临时阻塞
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001383
Oliver Keszöcze, R. Wille, R. Drechsler
{"title":"Exact routing for digital microfluidic biochips with temporary blockages","authors":"Oliver Keszöcze, R. Wille, R. Drechsler","doi":"10.1109/ICCAD.2014.7001383","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001383","url":null,"abstract":"Digital microfluidic biochips enable a higher degree of automation in laboratory procedures in biochemistry and molecular biology and have received significant attention in the recent past. Their design is usually conducted in several stages with routing being a particularly critical challenge. Previously proposed solutions for this design step suffer from two issues: They are mainly of heuristic nature and usually assume that the blockages to be bypassed are present the entire time. In contrast, we present a methodology which exploits the fact that blockages are often only present at certain intervals. At the same time, our approach guarantees exact solutions, i.e. always determines a routing with a minimal number of time steps. Experimental results show that, despite the huge complexity, optimal results can be achieved in reasonable run-time and that the consideration of temporary blockages indeed significantly improves the routing results.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124902264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
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