S. Hussain, Sudha Yellapantula, Mehrdad Majzoobi, F. Koushanfar
{"title":"BIST-PUF: Online, hardware-based evaluation of physically unclonable circuit identifiers","authors":"S. Hussain, Sudha Yellapantula, Mehrdad Majzoobi, F. Koushanfar","doi":"10.1109/ICCAD.2014.7001347","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001347","url":null,"abstract":"Physical Unclonable Functions (PUF) are of increasing importance due to their many hardware security applications including chip fingerprinting, metering, authentication, anti-counterfeiting, and supply-chain tracing, e.g., DARPA SHIELD. This paper presents BIST-PUF, the first built-in-self-test (BIST) methodology for online evaluation of weak and strong PUFs. BIST-PUF provides a paradigm shift in the evaluation of the un-clonable circuit identifiers: unlike earlier known PUF evaluation suites that are software-based and offline, BIST-PUF enables on-the-fly assessment of the desired PUF properties all in hardware. More specifically, the BIST-PUF structure is designed to evaluate two main properties of PUFs, namely unpredictability and stability. These properties are important for ensuring robustness and security in face of operational, structural, and environmental fluctuations due to variations, aging or adversarial acts. For BIST-PUF unpredictability evaluation, we identify and adopt the tests of randomness that are amenable to hardware implementation. For stability assessment, the BIST-PUF suggests three distinct methods, namely, sensor-based, parametric interrogation, and multiple interrogations. Proof-of-concept implementation of the BIST-PUF in FPGA demonstrates its low overhead, effectiveness, and practicality.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131378180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication","authors":"Hantao Huang, Sai Manoj Pudukotai Dinakarrao, Dongjun Xu, Hao Yu, Zhigang Hao","doi":"10.1109/ICCAD.2014.7001356","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001356","url":null,"abstract":"A reinforcement learning based I/O management is developed for energy-efficient communication between many-core microprocessor and memory. Instead of transmitting data under a fixed large voltage-swing, an online reinforcement Q-learning algorithm is developed to perform a self-adaptive voltage-swing control of 2.5D through-silicon interposer (TSI) I/O circuits. Such a voltage-swing adjustment is formulated as a Markov decision process (MDP) problem solved by model-free reinforcement learning under constraints of both power budget and bit-error-rate (BER). Experimental results show that the adaptive 2.5D TSI I/Os designed in 65nm CMOS can achieve an average of 12.5mw I/O power, 4GHz bandwidth and 3.125pJ/bit energy efficiency for one channel under 10-6 BER, which has 18.89% power saving and 15.11% improvement of energy efficiency on average.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132666571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BDD-based synthesis of reconfigurable single-electron transistor arrays","authors":"Zheng Zhao, Chian-Wei Liu, Chun-Yao Wang, Weikang Qian","doi":"10.1109/ICCAD.2014.7001328","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001328","url":null,"abstract":"Single-electron transistor (SET) is an ultra-low power device, which has been demonstrated as a promising alternative for CMOS devices in reducing power consumption. A suitable structure for realizing logic function using SET is a binary decision diagram (BDD)-based SET array. Previous works proposed product term-based automated synthesis methods to map a given logic function onto an SET array. In this work, we propose a novel BDD-based synthesis method that exploits the structure similarity between an SET array and a BDD. Our method transforms a BDD of a Boolean function into a planar graph and further maps the graph onto an SET array. Experiment results showed that compared to the state-of-the-art synthesis method, our method saves 51% in area on average and is more than 16 times faster.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132722564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Banerjee, B. Muldrey, Shreyas Sen, Xian Wang, A. Chatterjee
{"title":"Self-learning MIMO-RF receiver systems: Process resilient real-time adaptation to channel conditions for low power operation","authors":"D. Banerjee, B. Muldrey, Shreyas Sen, Xian Wang, A. Chatterjee","doi":"10.1109/ICCAD.2014.7001430","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001430","url":null,"abstract":"Prior research has established that dynamically trading-off the performance of the RF front-end for reduced power consumption across changing channel conditions, using a feedback control system that modulates circuit and algorithmic level \"tuning knobs\" in real-time, leads to significant power savings. It is also known that the optimal power control strategy depends on the process conditions corresponding to the RF devices concerned. This complicates the problem of designing the feedback control system that guarantees the best control strategy for minimizing power consumption across all channel conditions and process corners. Since this problem is largely intractable due to the complexity of simulation across all channel conditions and process corners, we propose a self-learning strategy for adaptive MIMO-RF systems. In this approach, RF devices learn their own performance vs. power consumption vs. tuning knob relationships \"on-the-fly\" and formulate the optimum reconfiguration strategy using neural-network based learning techniques during real-time operation. The methodology is demonstrated for a MIMO-RF receiver front-end and is supported by hardware validation leading to 2.5X power savings in minimal learning time.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132295328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data-aware DRAM refresh to squeeze the margin of retention time in hybrid memory cube","authors":"Yinhe Han, Ying Wang, Huawei Li, Xiaowei Li","doi":"10.1109/ICCAD.2014.7001366","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001366","url":null,"abstract":"With the increase of storage density, DRAM refresh leads to higher overhead of power and bandwidth, particularly in emerging 3D stacked memory design like Hybrid Memory Cube (HMC). To exploit the hardware resources for a smarter solution, we propose a data-aware refresh control scheme, Trial and Error (Trial-n-Error), which leverages the data-pattern dependence characteristics of the cells' retention time to reduce refresh operations. Trial-n-Error is a systematic approach that employs our proposed Synergy Testing to capture the refresh bottleneck of DRAM memory: “weak” cells that have a relatively shorter retention time. By locating the dominant weak cells sensitized by applications, Trial-n-Error can avoid the worst-case refresh setting, and adjust the refresh rate under the control of our self-tuning algorithm. Thus, Trial-n-Error can gradually approach to the possible lower-bound of refresh rate for less energy and memory bandwidth consumption. In experiments of 3D-stacked DRAMs, we successfully eliminate an average of 28% refresh operations and save 21% refresh energy for a set of pre-profiled synthetic data patterns and real benchmarks.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134445951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IR-drop based electromigration assessment: Parametric failure chip-scale analysis","authors":"V. Sukharev, Xin Huang, Hai-Bao Chen, S. Tan","doi":"10.1109/ICCAD.2014.7001387","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001387","url":null,"abstract":"This paper presents a novel approach and techniques for electromigration (EM) assessment in power delivery networks. An increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect segments, is considered as a failure criterion. This criterion replaces a currently employed conservative weakest segment criterion, which does not account an essential redundancy for current propagation existing in the power-ground (p/g) networks. EM-induced increase in the resistance of the individual grid segments is described in the approximation of the physics-based formalism for void nucleation and growth. A developed technique for calculating the hydrostatic stress distribution inside a multi branch interconnect tree allows to avoid over optimistic prediction of the time to failure made with the Blech-Black analysis of individual branches of interconnect segment. Experimental results obtained on the IBM benchmark circuit validate the proposed methods.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132571621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting","authors":"S. H. Choday, K. Kwon, K. Roy","doi":"10.1109/ICCAD.2014.7001402","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001402","url":null,"abstract":"The recent advances in thin-film thermoelectric (TE) materials have created opportunities for on-chip cooling and energy-harvesting with heat-fluxes >100W/cm2. However, it remains unclear how effective these materials are in the context of realistic microprocessor floorplan and workloads. Moreover, these TE materials suffer from contact parasitics that can significantly impact their performance. To evaluate the workload dependent performance of on-chip TE devices, we developed a hierarchical simulation methodology that connects an architectural simulator and a power estimation tool with a thermal simulator capable of simulating TE devices. The well-known HotSpot thermal simulator is modified to incorporate TE equations along with contact parasitics in the TE module. SimpleScalar and McPAT were used to generate the runtime power of different functional units in an Out-of-Order processor across the SPEC2000 workloads. The power-map generated by McPAT is used by our TE enhanced HotSpot simulator to evaluate the cooling and harvesting capabilities of on-chip TE modules. Our results indicate that it is possible to obtain 11°C peak cooling at the hot-spots, or harvest upto 85mW of power from the hot-spots. We also show that on-chip TE devices can aid in boosting the clock frequency of the processor from 1200MHz to 1600MHz under iso-temperature comparison with the no-TE case. This framework also allows for the rapid design space exploration of TE module's material/physical parameters and the optimum placement options for the TE module on the chip floorplan.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125492971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multithreaded pipeline synthesis for data-parallel kernels","authors":"Mingxing Tan, B. Liu, Steve Dai, Zhiru Zhang","doi":"10.1109/ICCAD.2014.7001431","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001431","url":null,"abstract":"Pipelining is an important technique in high-level synthesis, which overlaps the execution of successive loop iterations or threads to achieve high throughput for loop/function kernels. Since existing pipelining techniques typically enforce in-order thread execution, a variable-latency operation in one thread would block all subsequent threads, resulting in considerable performance degradation. In this paper, we propose a multithreaded pipelining approach that enables context switching to allow out-of-order thread execution for data-parallel kernels. To ensure that the synthesized pipeline is complexity effective, we further propose efficient scheduling algorithms for minimizing the hardware overhead associated with context management. Experimental results show that our proposed techniques can significantly improve the effective pipeline throughput over conventional approaches while conserving hardware resources.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122401938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs","authors":"Yu-Chen Chen, Sheng-Yen Chen, Yao-Wen Chang","doi":"10.1109/ICCAD.2014.7001421","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001421","url":null,"abstract":"As FPGA architecture evolves, complex heterogenous blocks, such as RAMs and DSPs, are widely used to effectively implement various circuit applications. These complex blocks often consist of datapath-intensive circuits, which are not adequately addressed in existing packing and placement algorithms. Besides, scalability has become a first-order metric for modern FPGA design, mainly due to the dramatically increasing design complexity. This paper presents efficient and effective packing and analytical placement algorithms for large-scale heterogeneous FPGAs to deal with issues on heterogeneity, datapath regularity, and scalability. Compared to the well-known academic tool VPR, experimental results show that our packing and placement algorithms achieve respective 199.80X and 3.07X speedups with better wirelength, and our overall flow achieves 50% shorter wirelength, with an 18.30X overall speedup.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yan Fang, V. Yashin, Andrew J. Seel, Brandon B. Jennings, Reggie Barnett, D. Chiarulli, S. Levitan
{"title":"Modeling oscillator arrays for video analytic applications","authors":"Yan Fang, V. Yashin, Andrew J. Seel, Brandon B. Jennings, Reggie Barnett, D. Chiarulli, S. Levitan","doi":"10.1109/ICCAD.2014.7001336","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001336","url":null,"abstract":"Weakly coupled oscillators have shown promise as a computational building block that exploits the power of emerging low power high density nano-devices such as spin torque oscillators and vanadium oxide oscillators. In this paper, we develop a new analytic phase model as well as a circuit simulation to show how clusters and arrays of coupled oscillators can be inserted into three different stages of an image processing pipeline and provide comparable image recognition performance to traditional methods.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128069335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}