BDD-based synthesis of reconfigurable single-electron transistor arrays

Abstract

Single-electron transistor (SET) is an ultra-low power device, which has been demonstrated as a promising alternative for CMOS devices in reducing power consumption. A suitable structure for realizing logic function using SET is a binary decision diagram (BDD)-based SET array. Previous works proposed product term-based automated synthesis methods to map a given logic function onto an SET array. In this work, we propose a novel BDD-based synthesis method that exploits the structure similarity between an SET array and a BDD. Our method transforms a BDD of a Boolean function into a planar graph and further maps the graph onto an SET array. Experiment results showed that compared to the state-of-the-art synthesis method, our method saves 51% in area on average and is more than 16 times faster.