2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第4页

Thermal-aware synthesis of integrated photonic ring resonators 集成光子环谐振器的热感知合成

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.5555/2691365.2691476

Christopher Condrat, P. Kalla, S. Blair

{"title":"Thermal-aware synthesis of integrated photonic ring resonators","authors":"Christopher Condrat, P. Kalla, S. Blair","doi":"10.5555/2691365.2691476","DOIUrl":"https://doi.org/10.5555/2691365.2691476","url":null,"abstract":"Photonic ring-resonators are key components of many on-chip optical-interconnect wavelength division multiplexing (WDM) network architectures. Thermal interactions between on-chip heat-sources and ring resonators pose significant operational and integration challenges, as these devices are extremely sensitive to temperature-induced changes in refractive index. Contemporary literature proposes active compensation for such refractive index variations (e.g. carrier-injection based tuning and/or WDM channel remapping); however, these are costly in terms of power and area. This paper presents a thermal-aware synthesis approach for ring-resonator compensation. We show how ring-resonators are analyzed in the presence of external thermal gradients, and employ a perturbation analysis to derive an equivalent, trimming-enabled, ring-resonator design. Our methodology produces a design-template that can be used to compensate for thermal variations through modifications to the waveguide's geometric structure. This approach complements active compensation techniques, and the synthesis is compatible with contemporary lithographic methods. Using this approach, we perform design space exploration with respect to variations to the waveguide structure and their effect on the range and precision of thermal compensation.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121084593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Multiple clock domain synchronization in a QBF-based verification environment 基于qbf验证环境下的多时钟域同步

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001426

Djordje Maksimovic, Bao Le, A. Veneris

{"title":"Multiple clock domain synchronization in a QBF-based verification environment","authors":"Djordje Maksimovic, Bao Le, A. Veneris","doi":"10.1109/ICCAD.2014.7001426","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001426","url":null,"abstract":"Modern designs are growing in size and complexity, becoming increasingly harder to verify. Today, they are architected to include multiple clock domains as a measure to reduce power consumption. Verifying them proves to be a computationally intensive and challenging task as it requires their clocks to be synchronized. To achieve synchronization, existing Boolean satisfiability-based methodologies add hardware to combine the clock domains before transforming them into their iterative logic array representation (ILA). As a consequence, this results in the addition of redundant time-frames adding overhead during verification. This paper introduces a novel framework to verify designs with multiple clocks using Quantified Boolean Formula satisfiability (QBF). We first present a formulation that models an ILA representation with symbolic universal quantification to achieve synchronization. This is later extended with the use of a clock divider to overcome inefficiencies. The net effect is the reduction in the number of redundant time-frames. Furthermore, the usage of QBF results in significant memory savings when compared to traditional methods. Experiments on bounded model checking demonstrate memory reductions of 76% on average with competitive run-time performance.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127775958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Towards a rich sensing stack for IoT devices 面向物联网设备的丰富传感堆栈

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001386

Chenguang Shen, Haksoo Choi, Supriyo Chakraborty, M. Srivastava

{"title":"Towards a rich sensing stack for IoT devices","authors":"Chenguang Shen, Haksoo Choi, Supriyo Chakraborty, M. Srivastava","doi":"10.1109/ICCAD.2014.7001386","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001386","url":null,"abstract":"The broad spectrum of interconnected sensors and actuators, available on various mobile devices and smartphones and collectively defined as the Internet of Things (IoT), have evolved into platforms with ability to both collect personal sensory data and also change the users' immediate environment. The continuous streams of richly annotated sensory data on these IoT devices have also enabled the emergence of a new class of context-aware apps that use the data to infer user context and accordingly customize their responses in real-time. However, this growth in the number of apps has not been complemented with adequate system support on the IoT devices resulting in monolithic apps that each implement and execute their own customized sensing pipelines. In this paper, we outline our vision of a sensing stack, akin to a networking stack, that can facilitate the development and execution of context-aware apps on IoT devices. There are several advantages to building a rich sensing stack. First, it allows apps to reuse stages of the sensing pipeline easing their development. Second, the layers of the stack allow for both in- and cross-layer resource optimization. Finally, it allows better control over the shared data as instead of raw-sensor data, higher-level semantic abstractions, such as inferences can now be shared with apps. We describe our initial efforts towards creating the different building blocks of such a sensing stack.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114459403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Improving the efficiency of automated debugging of pipelined microprocessors by symmetry breaking in modular schemes for Boolean encoding of cardinality 在基数布尔编码的模块化方案中采用对称性破缺，提高了流水线微处理器自动调试的效率

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001425

M. Velev, Ping Gao

引用次数: 0

Sub-20 nm design technology co-optimization for standard cell logic sub - 20nm设计技术协同优化标准电池逻辑

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001342

Kaushik Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi

{"title":"Sub-20 nm design technology co-optimization for standard cell logic","authors":"Kaushik Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi","doi":"10.1109/ICCAD.2014.7001342","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001342","url":null,"abstract":"Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. Conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology offerings, we propose a holistic design technology co-optimization (DTCO) for standard cell logic. In our holistic DTCO we co-optimize the standard cell architecture to balance manufacturability and efficiency at the cell level while taking into account block level considerations such as pin accessibility and power rail robustness. Our DTCO in a foundry 14 nm CMOS resulted in two standard cell architectures, namely, 10T_BiDir and 10T_UniDir. We evaluated these cell libraries with physically synthesized blocks and ring oscillator test structures in IBM 14SOI process. We observed that 10T_BiDir emerges as the preferred alternative at 14 nm CMOS, with 10T_UniDir promising better scalability to future nodes.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124962223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Overlapping-aware throughput-driven stencil planning for E-beam lithography 电子束光刻中可感知重叠的吞吐量驱动模板规划

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.5555/2691365.2691416

Jian Kuang, Evangeline F. Y. Young

{"title":"Overlapping-aware throughput-driven stencil planning for E-beam lithography","authors":"Jian Kuang, Evangeline F. Y. Young","doi":"10.5555/2691365.2691416","DOIUrl":"https://doi.org/10.5555/2691365.2691416","url":null,"abstract":"E-Beam Lithography (EBL) is a maskless nano-lithography technology that creates features on a wafer by directly shooting a beam of electrons onto the wafer. Different from the current mainstream optical lithography technology, i.e. 193nm ArF immersion lithography, EBL overcomes the limit of light diffraction. As one of the most promising next generation lithography (NGL) technologies, it can achieve very high resolution even for sub-10nm technology node. However, before EBL can be used for High Volume Manufacturing (HVM), its problem of low throughput has to be solved. Character Projection (CP) with a set of pre-defined characters is thought to be an essential technology for throughput improvement. With CP, a key problem is stencil planning, which is to select and place the best characters onto the stencil such that the throughput of the system can be maximized. If the overlapping between characters are awared, the throughput can be further optimized. In this paper, we investigate this 2D overlapping-aware stencil planning problem. Experiments show that our approach can achieve significant throughput improvement and remarkable speed-up comparing with previous works.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124674954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Triple patterning aware detailed placement with constrained pattern assignment 具有约束模式分配的三重模式感知详细布局

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001341

Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong

{"title":"Triple patterning aware detailed placement with constrained pattern assignment","authors":"Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong","doi":"10.1109/ICCAD.2014.7001341","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001341","url":null,"abstract":"Triple patterning lithography (TPL) has been recognized as one of the most promising techniques for 14/10nm technology node. There are various concerns for TPL decompositions. For standard cell based designs, assigning the same pattern for the same type of cells is a desired property for TPL decomposition. It is more robust for process variations and gives the chip similar physical and electrical characteristics as well as more reliable and predictable performance. Assigning the same type of pattern for the same type of cell is called a constrained pattern assignment (CPA) problem. In this paper, we integrated the flow of detailed placement and TPL decompositions with CPA coloring constraints. We focused on refining a layout to make it CPA-friendly during the detailed placement stage while minimizing the area and HPWL (half perimeter wire length) overhead. A weighted partial MAX SAT approach is proposed which guarantees to obtain a CPA-friendly detailed placement result while minimizing the area overhead. An efficient graph model is also proposed to compute the locations of the cells with optimal HPWL. Our formulation is very efficient and achieves a 79.4% area overhead reduction compared with the approach of fixing cell colors beforehand. Better HPWL are also achieved consistently over all benchmarks.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129949669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

A learning-on-cloud power management policy for smart devices 智能设备的云上学习电源管理策略

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001379

Gung-Yu Pan, B. Lai, Sheng-Yen Chen, Jing-Yang Jou

引用次数: 8

Silicon fault diagnosis using sequence interpolation with backbones 带主干序列插值的硅故障诊断

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001373

C. Zhu, Georg Weissenbacher, S. Malik

{"title":"Silicon fault diagnosis using sequence interpolation with backbones","authors":"C. Zhu, Georg Weissenbacher, S. Malik","doi":"10.1109/ICCAD.2014.7001373","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001373","url":null,"abstract":"Silicon fault diagnosis, the process of locating faults in a chip prototype, becomes more challenging and time-consuming with increasing design complexity. Consistency-based fault diagnosis aims at identifying fault candidates for an erroneous execution trace by symbolically checking the consistency between the golden gate-level model and the faulty behavior of the prototype chip. The scalability of this technique is limited to short executions due to the underlying decision procedure. This problem has previously been addressed by restricting the analysis to a window of fixed size and moving it along the execution trace. In this setting, limited observability results in a loss of precision and potentially missed fault candidates. We present a novel interpolation-based framework which formalizes the propagation of state information across sliding windows as a satisfiability problem. Our approach provides both spatial and temporal localization for general faults and is not restricted to a specific fault model. Further, our approach can be used to provide more accurate localization for a single permanent fault model. We experimentally demonstrate the efficacy and scalability of this approach by applying it to a variety of benchmarks from multiple suites (OpenCores, ITC99 and HWMCC).","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132417325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Probabilistic model checking for comparative analysis of automated air traffic control systems 自动空中交通管制系统比较分析的概率模型检验

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001427

Yang Zhao, Kristin Yvonne Rozier

{"title":"Probabilistic model checking for comparative analysis of automated air traffic control systems","authors":"Yang Zhao, Kristin Yvonne Rozier","doi":"10.1109/ICCAD.2014.7001427","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001427","url":null,"abstract":"Ensuring aircraft stay safely separated is the primary consideration in air traffic control. To achieve the required level of assurance for this safety-critical application, the Automated Airspace Concept (AAC) proposes a network of components providing multiple levels of separation assurance, including conflict detection and resolution. In our previous work, we conducted a formal study of this concept including specification, validation, and verification utilizing the NuSMV and CadenceSMV model checkers to ensure there are no potentially catastrophic design flaws remaining in the AAC design before the next stage of production. In this paper, we extend that work to include probabilistic model checking of the AAC system.1 We are motivated by the system designers requirement to compare different design options to optimize the functional allocation of the AAC components. Probabilistic model checking provides quantitative measures for evaluating different design options, helping system designers to understand the impact of parameters in the model on a given critical safety requirement. We detail our approach to modeling and probabilistically analyzing this complex system consisting of a real-time algorithm, a logic protocol, and human factors. We utilize both Discrete Time Markov Chain (DTMC) and Continuous Time Markov Chain (CTMC) models to capture the important behaviors in the AAC components. The separation assurance algorithms, which are defined over specific time ranges, are modeled using a DTMC. The emergence of conflicts in an airspace sector and the reaction times of pilots, which can be simplified as Markov processes on continuous time, are modeled as a CTMC. Utilizing these two models, we calculate the probability of an unresolved conflict as a measure of safety and compare multiple design options.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115157150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20