2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第10页

Security of IoT systems: Design challenges and opportunities 物联网系统的安全性:设计挑战与机遇

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001385

T. Xu, James Bradley Wendt, M. Potkonjak

{"title":"Security of IoT systems: Design challenges and opportunities","authors":"T. Xu, James Bradley Wendt, M. Potkonjak","doi":"10.1109/ICCAD.2014.7001385","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001385","url":null,"abstract":"Computer-aided design (CAD), in its quest to facilitate new design revolutions, is again on the brink of changing its scope. Following both historical and recent technological and application trends, one can identify several emerging research and development directions in which CAD approaches and techniques may have major impacts. Among them, due to the potential to fundamentally alter everyday life as well as how science and engineering systems are designed and operated, the Internet of Things (IoT) stands out. IoT also poses an extraordinary system replete with conceptual and technical challenges. For instance, greatly reduced quantitative bounds on acceptable area and energy metrics require qualitative breakthroughs in design and optimization techniques. Most likely the most demanding of requirements for the widespread realization of many IoT visions is security. IoT security has an exceptionally wide scope in at least four dimensions. In terms of security scope it includes rarely addressed tasks such as trusted sensing, computation, communication, privacy, and digital forgetting. It also asks for new and better techniques for the protection of hardware, software, and data that considers the possibility of physical access to IoT devices. Sensors and actuators are common components of IoT devices and pose several unique security challenges including the integrity of physical signals and actuating events. Finally, during processing of collected data, one can envision many semantic attacks. Our strategic objective is to provide an impetus for the development of IoT CAD security techniques. We start by presenting a brief survey of IoT challenges and opportunities with an emphasis on security issues. Next, we discuss the potential of hardware-based IoT security approaches. Finally, we conclude with several case studies that advocate the use of stable PUFs and digital PPUFs for several IoT security protocols.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121408657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 322

Security-aware mapping for TDMA-based real-time distributed systems 基于tdma的实时分布式系统的安全感知映射

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001325

Chung-Wei Lin, Qi Zhu, A. Sangiovanni-Vincentelli

{"title":"Security-aware mapping for TDMA-based real-time distributed systems","authors":"Chung-Wei Lin, Qi Zhu, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCAD.2014.7001325","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001325","url":null,"abstract":"Cyber-security has become a critical issue for realtime distributed embedded systems in domains such as automotive, avionics, and industrial automation. However, in many of such systems, tight resource constraints and strict timing requirements make it difficult or even impossible to add security mechanisms after the initial design stages. To produce secure and safe systems with desired performance, security must be considered together with other objectives at the system level and from the beginning of the design. In this paper, we focus on security-aware design for Time Division Multiple Access (TDMA) based real-time distributed systems. The TDMA-based protocol we consider is an abstraction of many time-triggered protocols that are being adopted in various safety-critical systems for their more predictable timing behavior, such as FlexRay, Time-Triggered Protocol, and Time-Triggered Ethernet. To protect against attacks on TDMA-based real-time distributed systems, we apply a message authentication mechanism with time-delayed release of keys, which provides a good balance between security and computational overhead but needs sophisticated network scheduling to ensure that the increased latencies due to delayed key releases will not violate timing requirements. We propose formulations and an algorithm to optimize the task allocation, priority assignment, network scheduling, and key-release interval length during the mapping process, while meeting both security and timing requirements. Experimental results of an automotive case study and a synthetic example show the effectiveness and efficiency of our approach.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116345788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

Protecting integrated circuits from piracy with test-aware logic locking 通过测试感知逻辑锁定保护集成电路免受盗版

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001361

Stephen M. Plaza, I. Markov

引用次数: 23

DRC-based hotspot detection considering edge tolerance and incomplete specification 考虑边缘容差和不完全规格的基于drc的热点检测

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001339

Yen-Ting Yu, I. Jiang, Yumin Zhang, C. Chiang

{"title":"DRC-based hotspot detection considering edge tolerance and incomplete specification","authors":"Yen-Ting Yu, I. Jiang, Yumin Zhang, C. Chiang","doi":"10.1109/ICCAD.2014.7001339","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001339","url":null,"abstract":"To improve the yield in current manufacturing processes, the problematic layout configurations, so-called process-hotspots, should be detected and replaced with yield friendly patterns. A hotspot pattern with edge tolerances and incomplete specifications, where edges may vary in a certain range and any layout configurations may exist in its ambit regions, can sufficiently and generally represent a process-hotspot. This type of hotspots, however, cannot be efficiently or correctly detected by using the state-of-the-art string-matching-based method. In this paper, we present an accurate and efficient DRC-based hotspot detection framework to handle hotspot patterns with edge tolerances and incomplete specifications. Unlike existing DRC-based work, which handles only completely specified patterns, we extract critical design rules to represent all possible topologies of hotspot patterns with edge tolerances and incomplete specifications. We further order these rules to iteratively reduce the search regions of a layout during design rule checking. Then, we apply longest common subsequence and linear scan to locate all hotspots accurately and efficiently. Compared with the state-of-the-art work, experimental results show that our approach can reach promising success rates with significant speedups.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132302061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Validating direct memory access interfaces with conformance checking 通过一致性检查验证直接内存访问接口

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001323

Li Lei, Kai Cong, Zhenkun Yang, Fei Xie

{"title":"Validating direct memory access interfaces with conformance checking","authors":"Li Lei, Kai Cong, Zhenkun Yang, Fei Xie","doi":"10.1109/ICCAD.2014.7001323","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001323","url":null,"abstract":"Direct Memory Access (DMA) interfaces are a common and important component of Hardware/Software (HW/SW) interfaces between peripheral devices and their device drivers. We present a HW/SW co-validation framework to validate DMA interface implementations of a device and its driver. This framework employs a virtual prototype of the device as a reference model and performs co-validation in two stages: (1) conformance checking which checks the DMA interface conformance between the device and its virtual prototype; (2) property checking which checks device/driver interactions across the DMA interface. In conformance checking, the virtual prototype infers the device state transitions by taking the same driver request sequence to the device. Property checking verifies system properties over the device state transitions exposed through the virtual prototype. This framework assists HW/SW integration validation by detecting DMA interface bugs in both devices and drivers. Furthermore, we have developed three key techniques: capture-on-write policy, partial capture, and environmental input prediction, to address two major challenges in scaling the framework: DMA capture overhead and imprecise environmental input simulation. We have applied this approach to four Ethernet adapters, discovering 12 serious DMA interface bugs from the devices, their virtual prototypes and their drivers. The results demonstrate that our approach has major potential in facilitating HW/SW co-validation.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126501238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

High-radix on-chip networks with low-radix routers 带有低基数路由器的高基数片上网络

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001365

Animesh Jain, Ritesh Parikh, V. Bertacco

{"title":"High-radix on-chip networks with low-radix routers","authors":"Animesh Jain, Ritesh Parikh, V. Bertacco","doi":"10.1109/ICCAD.2014.7001365","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001365","url":null,"abstract":"Networks-on-chip (NoCs) have become increasingly widespread in recent years due to the extensive integration of many components in modern multicore processors and SoC designs. One of the fundamental tradeoffs in NoC design is the radix of its constituent routers. While high-radix routers enable a richly connected and low diameter network, low-radix routers allow for a small silicon area. Since the NoC consumes a significant portion of the on-chip resources, naïvely deploying an expensive high-radix network is not a practical option. In this work, we present a novel solution to provide high-radix like performance at a cost similar to that of a low-radix network. Our solution leverages the irregularity in runtime communication patterns to provide short low-latency paths between frequently communicating nodes, while infrequently communicating pairs rely on longer paths. To this end, it leverages a flexible topology reconfiguration infrastructure with abundantly available links between routers (in accordance to a high-radix topology) that are decoupled from scarcely available router ports (similar to a low-radix topology). Network links are bound to router ports at runtime to form connected and deadlock-free topologies. Binding selections are based on the traffic patterns observed, which are synthesized through a distributed statistics-collection framework. Our experiments on a 64-node CMP, running multiprogrammed workloads, show that we can reduce average network latency by 19% over an area- and power- comparable mesh NoC. The latency improvements for non-uniform synthetic traffic are above 30%.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128525453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

MCFRoute: A detailed router based on multi-commodity flow method mcroute:一种基于多商品流方法的详细路由器

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001382

Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li

{"title":"MCFRoute: A detailed router based on multi-commodity flow method","authors":"Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li","doi":"10.1109/ICCAD.2014.7001382","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001382","url":null,"abstract":"Detailed routing is an important stage in VLSI physical design. Due to the high routing complexity, it is difficult for existing routing methods to guarantee total completion without design rule checking violations (DRCs) and it generally takes several days for designers to fix remaining DRC-s. Studies has shown that the low routing quality partly results from non-optimal net-ordering nature of traditional sequential methods. In this paper, a novel concurrent detailed routing algorithm is presented that overcomes the net-order problem. Based on the multi-commodity flow (M-CF) method, detailed routing problem with complex design rule constraints is formulated as an integer linear programming (ILP) problem. Experiments show that the proposed algorithm is capable of reducing design rule violations while introducing no negative effects on wirelength and via count. Implemented as a detailed router following track assignment, the algorithm can reduce the DRCs by 38%, meantime, wirelength and via count are reduced by 3% and 2.7% respectively comparing with an industry tool. Additionally, the algorithm is adopted as an incremental detailed router to refine a routing solution, and experimental results show that the number of DRCs that industry tool can't fix are further reduce by half. Utilizing the independency between subregions, an efficient parallelization algorithm is implemented that can get a close to linear speedup.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116830956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Real time anomaly detection in wide area monitoring of smart grids 智能电网广域监测中的实时异常检测

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-01 DOI: 10.1109/ICCAD.2014.7001352

Jie Wu, Jinjun Xiong, Prasenjit Shil, Yiyu Shi

{"title":"Real time anomaly detection in wide area monitoring of smart grids","authors":"Jie Wu, Jinjun Xiong, Prasenjit Shil, Yiyu Shi","doi":"10.1109/ICCAD.2014.7001352","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001352","url":null,"abstract":"The real time anomaly detection in wide area monitoring of smart grids is critical to enhance the reliability of power systems. However, capturing the features of anomalous interruption and then detecting them at real time is difficult for large-scale smart grids, because the measurement data volume and complexity increases drastically with the exponential growth of data from the immense intelligent monitoring devices to be rolled out and the need for fast information retrieval from those mass data. Most of existing anomaly detection methods fail to handle it well. This paper proposes a spatial-temporal correlation based anomalous behavior model to capture the characteristics of anomaly such as transmission line outages in smart grid. Inspired by Ledoit-Wolf Shrinkage (LWS) method, we develop the real time anomaly detection (ReTAD) algorithm to overcome the issue of gigantic measurement data volume. The proposed algorithm is not only suitable for large number of power systems with high dimensional measurement data, but at the same time is also low computational complexity to apply for real time detection. Using 14-, 30, and 2383-bus systems, our experimental study demonstrates that our proposed ReTAD algorithm successfully detects the anomalous events at real time.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122135031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

ICCAD-2014 CAD contest in incremental timing-driven placement and benchmark suite: Special session paper: CAD contest ICCAD-2014增量时间驱动布局和基准套件的CAD竞赛:特别会议论文:CAD竞赛

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-01 DOI: 10.1109/ICCAD.2014.7001376

Myung-Chul Kim, J. Huj, Natarajan Viswanathan

引用次数: 21

Common path pessimism removal: An industry perspective: Special Session: Common Path Pessimism Removal 消除普遍悲观情绪:行业视角:特别会议:消除普遍悲观情绪

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-01 DOI: 10.1109/ICCAD.2014.7001412

V. Garg

{"title":"Common path pessimism removal: An industry perspective: Special Session: Common Path Pessimism Removal","authors":"V. Garg","doi":"10.1109/ICCAD.2014.7001412","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001412","url":null,"abstract":"Process parameters, e.g., transistor width, may greatly vary not only across multiple manufacturing lots, but also within the same die from the same manufacturing lot. In addition to process variations different parts of a chip may see different voltages and temperatures. These process-voltage-temperature (PVT) variations are termed as On-Chip Variations (OCV) and can unsystematically affect wire and cell delays. This variability is accounted for by adding OCV de-ratings to path delays during static timing analysis (STA), where the original timing values are split into early (lowerbound) and late (upperbound) quantities. Chip timing is then done against these new delays to ensure safe chip operation. Any unknown or hard-to-model variation effect can also be margined for in these OCV de-ratings. However, this additional pessimism can significantly increase the difficulty to achieve timing closure, thereby elongating the design cycle and time to market. In particular, excess pessimism along clock network creates the most design-cycle churn, as pessimistic clock delays impact nearly all data paths. This session discusses the overview and challenges of common path pessimism removal (CPPR), the method of safely removing excess pessimism from clock paths, from an industry perspective.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127012973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4