Common path pessimism removal: An industry perspective: Special Session: Common Path Pessimism Removal

Abstract

Process parameters, e.g., transistor width, may greatly vary not only across multiple manufacturing lots, but also within the same die from the same manufacturing lot. In addition to process variations different parts of a chip may see different voltages and temperatures. These process-voltage-temperature (PVT) variations are termed as On-Chip Variations (OCV) and can unsystematically affect wire and cell delays. This variability is accounted for by adding OCV de-ratings to path delays during static timing analysis (STA), where the original timing values are split into early (lowerbound) and late (upperbound) quantities. Chip timing is then done against these new delays to ensure safe chip operation. Any unknown or hard-to-model variation effect can also be margined for in these OCV de-ratings. However, this additional pessimism can significantly increase the difficulty to achieve timing closure, thereby elongating the design cycle and time to market. In particular, excess pessimism along clock network creates the most design-cycle churn, as pessimistic clock delays impact nearly all data paths. This session discusses the overview and challenges of common path pessimism removal (CPPR), the method of safely removing excess pessimism from clock paths, from an industry perspective.