2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第9页

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems 可靠神经形态计算系统的还原和红外降补偿技术

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001330

Beiye Liu, Hai Helen Li, Yiran Chen, Xin Li, Tingwen Huang, Qing Wu, Mark D. Barnell

引用次数: 119

ReSCALE: Recalibrating sensor circuits for aging and lifetime estimation under BTI 重新校准传感器电路的老化和寿命估计下的BTI

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001396

Deepashree Sengupta, S. Sapatnekar

引用次数: 6

A novel linear algebra method for the determination of periodic steady states of nonlinear oscillators 一种确定非线性振子周期稳态的新线性代数方法

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001416

Haotian Liu, Kim Batselier, N. Wong

引用次数: 8

Data-parallel simulation for fast and accurate timing validation of CMOS circuits 数据并行仿真用于快速准确的CMOS电路时序验证

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001324

E. Schneider, S. Holst, X. Wen, H. Wunderlich

引用次数: 9

Fast statistical analysis of rare circuit failure events via subset simulation in high-dimensional variation space 基于高维变分空间子集仿真的罕见电路故障事件快速统计分析

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001370

Shupeng Sun, Xin Li

引用次数: 32

A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter 带抖动的高速I/O链路眼图可达性验证的分区宏建模

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001428

Sai Manoj Pudukotai Dinakarrao, Hao Yu, Chenjie Gu, Cheng Zhuo

引用次数: 0

Opportunistic through-silicon-via inductor utilization in LC resonant clocks: Concept and algorithms LC谐振时钟中机会通硅电感的应用:概念和算法

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001435

Umamaheswara Rao Tida, V. Mittapalli, Cheng Zhuo, Yiyu Shi

{"title":"Opportunistic through-silicon-via inductor utilization in LC resonant clocks: Concept and algorithms","authors":"Umamaheswara Rao Tida, V. Mittapalli, Cheng Zhuo, Yiyu Shi","doi":"10.1109/ICCAD.2014.7001435","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001435","url":null,"abstract":"LC resonant clock is an attracting option for low power on-chip clock distribution designs. However, a major limiting factor to its implementation is the large area overhead due to the conventional spiral inductors. On the other hand, idle through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D ICs) can form vertical inductors with minimal footprint and little noise coupling with horizontal traces, particularly suitable for the application of LC resonant clock. However, due to the strict constraints on the location of idle TSVs, the use of the TSV inductor is limited by the constrained choices of its location, inductance and quality factor. Moreover, these TSV inductors can be in any orientation with any distance apart, thereby causing complicated coupling effects. In this paper, we present a novel scheme to opportunistically use idle TSVs to form inductors in LC resonant clock of 3D ICs for maximum power reduction. We formulate the problem and devise a greedy algorithm to efficiently solve it. Experimental results on a few industrial designs show that compared with the conventional resonant clock designs using spiral inductors, our scheme with TSV inductors can reduce the inductor footprint by up to 6.30x with the same power consumption. Especially these TSV inductors are formed by existing idle TSVs so they essentially come for free. To the best of the authors' knowledge, this is the very first work to apply TSV inductors to the resonant CDN.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133445112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations 智能电网负载平衡技术通过同步开关/联络线/电线配置

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001380

I. Jiang, Gi-Joon Nam, Hua-Yu Chang, S. Nassif, J. Hayes

{"title":"Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations","authors":"I. Jiang, Gi-Joon Nam, Hua-Yu Chang, S. Nassif, J. Hayes","doi":"10.1109/ICCAD.2014.7001380","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001380","url":null,"abstract":"Fast changing power distribution systems request a dynamic system configuration capability of reacting to volatile consumption demands in an economical way. Load balancing in power distribution systems is an essential technique for smart grid that enables reliable electricity delivery to end customers. This paper is the first work focusing on load balancing using switch reconfiguration, tie-line addition, and wire upgrade simultaneously, while existing works adopt only one of the three techniques to configure the power distribution system. We observe that the new load balancing problem induces a new challenge, dynamic topology rotation, which cannot be handled by existing solutions. To overcome this challenge, we first consider bidirectional power flows and formulate the load balancing problem as a mixed-integer quadratically constrained quadratic program (MIQCQP). To reduce the computational complexity, it is further transformed into a mixed-integer linear program (MILP) without loss of optimality. Experimental results show that, on real power distribution networks, our approach produces optimal solutions that are unlikely to be found in ad-hoc heuristics methods.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"65 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114795479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Cellular neural networks for image analysis using steep slope devices 使用陡坡装置的细胞神经网络图像分析

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001337

Indranil Palit, Qiuwen Lou, M. Niemier, B. Sedighi, J. Nahas, X. Hu

{"title":"Cellular neural networks for image analysis using steep slope devices","authors":"Indranil Palit, Qiuwen Lou, M. Niemier, B. Sedighi, J. Nahas, X. Hu","doi":"10.1109/ICCAD.2014.7001337","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001337","url":null,"abstract":"Traditional CMOS based von Neumann architectures face daunting challenges in performing complex computational tasks at high speed and with low power on spatio-temporal data, e.g., image processing, pattern recognition, etc. In this study, we discuss the utilities of various steep slope, beyond-CMOS emerging devices for image processing applications within the non-von Neumann computing paradigm of cellular neural networks (CNNs). In general, the steep subthreshold swing of the devices obviates the output transfer hardware used in a conventional CNN cell. For image processing with binary stable outputs, Tunnelling FETs (TFETs) can facilitate low power operation. For multi-valued problems, devices like graphene transistors, Symmetric tunnelling FETs (SymFETs) might be leveraged to solve a problem with fewer computational steps. The potential for additional hardware reduction when compared to functional equivalents via conventional CNNs is also possible. Emerging devices can also lead to lower power implementations of the voltage controlled current sources (VCCSs) that are an integral component of any CNN cell. Furthermore, non-linear implementations of the VCCSs via emerging devices could enable simpler computational paths for many image processing tasks.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A non-volatile memory based physically unclonable function without helper data 一种基于非易失性内存的不带辅助数据的物理不可克隆函数

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001345

Wenjie Che, J. Plusquellic, S. Bhunia

{"title":"A non-volatile memory based physically unclonable function without helper data","authors":"Wenjie Che, J. Plusquellic, S. Bhunia","doi":"10.1109/ICCAD.2014.7001345","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001345","url":null,"abstract":"Stability across environmental variations such as temperature and voltage, is critically important for Physically Unclonable Functions (PUFs). Nearly all existing PUF systems to date need a mechanism to deal with “bit flips” when exact regeneration of the bitstring is required, e.g., for cryptographic applications. Error correction (ECC) and error avoidance schemes have been proposed but both of these require helper data to be stored for the regeneration process. Unfortunately, helper data adds time and area overhead to the PUF system and provides opportunities for adversaries to reverse engineer the secret bitstring. In this paper, we propose a non-volatile memory-based (NVM) PUF that is able to avoid bit flips without requiring any type of helper data. A voltage-to-digital converter technique is described for digitizing the analog entropy source and a robust median-finding algorithm is proposed as the reprograming strategy. Analysis on published experimental data is presented to demonstrate the practicability of our proposed strategy. We describe the technique in the context of emerging nano-devices, in particular, resistive random access memory (Memristor) cells, but the methodology is applicable to any type of NVM including Flash.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121217142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 60