{"title":"Design and technology co-optimization near single-digit nodes","authors":"L. Liebmann, R. Topaloglu","doi":"10.1109/ICCAD.2014.7001409","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001409","url":null,"abstract":"As we approach single-digit nodes, traditional design for manufacturability is augmented through several methodologies and design paradigms such as design-technology co-optimization (DTCO), systematic yield limiters optimization (SYLO), and design retargeting. We discuss triple-patterning and spacer-based multiple patterning and their design implications as these technologies will be necessary to cruise us to single-digit nodes. With the help of DTCO, there seems to be a clear path to sub-10nm with or without extreme ultra-violet lithography.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133860088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Full chip impact study of power delivery network designs in monolithic 3D ICs","authors":"S. Samal, K. Samadi, P. Kamal, Yang Du, S. Lim","doi":"10.1109/ICCAD.2014.7001406","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001406","url":null,"abstract":"In this paper, we present a comprehensive study on the impact of power delivery network (PDN) on full-chip wirelength, routability, power, and thermal effects in monolithic 3D ICs. Our studies first show that the full PDN worsens routing congestion more severely in monolithic 3D ICs than in 2D designs due to the significant reduction in resources for 3D connections. The increase in signal wirelength translates into additional net switching power dissipation, which significantly contributes to total power. This in turn aggravates thermal issues in 3D ICs. In addition, we observe that PDN tradeoffs among wirelength, power, and thermal are more pronounced in monolithic 3D ICs than TSV-based 3D and 2D designs. This is because of the higher integration density and the severe competition between signal and power connections. Lastly, we develop various PDN design optimization techniques for monolithic 3D ICs and obtain up to 8% signal wirelength and 5% maximum temperature reduction under the given IR drop budget.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121916444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal offloading control for a mobile device based on a realistic battery model and semi-Markov decision process","authors":"Shuang Chen, Yanzhi Wang, Massoud Pedram","doi":"10.1109/ICCAD.2014.7001378","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001378","url":null,"abstract":"Due to the limited battery capacity in mobile devices, the concept of mobile cloud computing (MCC) is proposed where some applications are offloaded from the local device to the cloud for higher energy efficiency. The portion of applications or tasks to be offloaded for remote processing should be judiciously determined. In this paper, the problem of optimal task dispatch, transmission, and execution in the MCC system is considered. Dynamic voltage and frequency scaling (DVFS) is applied to the local mobile processor, whereas the RF transmitter of the mobile device can choose from multiple modulation schemes and bit rates. The power consumptions of the mobile components that cannot be directly controlled, e.g., the touch screen, GPU, audio codec, and I/O ports, are also accounted for through capturing their correlation with the mobile processor and RF transmitter. Finally, a realistic and accurate battery model is adopted in this work in order to estimate the battery energy loss rate in a more accurate way. This paper presents a semi-Markov decision process (SMDP)-based optimization framework, with the actions of different DVFS levels and modulation schemes/transimission bit rates and the objective of minimizing both the energy drawn from the battery and the average latency in request servicing. This paper derives the optimal solution, including the optimal DVFS policy, offloading rate, and transmission scheme, using linear programming combined with a heuristic search. Experiments are conducted on Qualcomm Snapdragon Mobile Development Platform MSM8660 to find the correlations among the power consumptions of the CPU, RF components, and other components. Simulation results show that the proposed optimal solution consistently outperforms some baseline algorithms.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122022465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An efficient spectral graph sparsification approach to scalable reduction of large flip-chip power grids","authors":"Xueqian Zhao, Zhuo Feng, Cheng Zhuo","doi":"10.5555/2691365.2691410","DOIUrl":"https://doi.org/10.5555/2691365.2691410","url":null,"abstract":"Existing state-of-the-art realizable RC reduction methods may not be suitable for scalable power grid reductions due to the fast growing computational complexity and the large number of ports. In this work, we present a scalable power grid reduction method for reducing large-scale flip-chip power grids based on recent spectral graph sparsification techniques. The first step of the proposed approach aggressively reduces the large power grid blocks into much smaller power grid blocks by properly matching the effective resistances of the original power grid networks. Next, an efficient spectral graph sparsification scheme is introduced to dramatically sparsify the relatively dense power grid blocks that are generated during the previous step. In the last, an effective grid compensation scheme is proposed to further improve the model accuracy of the reduced and sparsified power grid. Since reduction of each power grid block can be performed independently, our method can be easily accelerated on parallel computers, and therefore expected to be capable of handling large power grid designs as well as incremental designs. Extensive experimental results show that our method can scale linearly with power grid sizes and efficiently reduce industrial power grids sizes by 20X without loss of much accuracy in both DC and transient analysis.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130074752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Frank A. Nothaft, Luis Fernandez, Stephen Cefali, Nishant Shah, J. Rael, Luke Darnell
{"title":"Pragma-based floating-to-fixed point conversion for the emulation of analog behavioral models","authors":"Frank A. Nothaft, Luis Fernandez, Stephen Cefali, Nishant Shah, J. Rael, Luke Darnell","doi":"10.1109/ICCAD.2014.7001419","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001419","url":null,"abstract":"Design teams have embraced hardware verification accelerators that enable pre-silicon firmware development. However, emulation is inapplicable for large mixed signal designs. We introduce a methodology that allows for the reuse of analog behavioral models in verification accelerators. We provide a set of pragmas that allow real number models to be converted to fixed point and synthesized and introduce an approach for demonstrating the correctness of these models. We demonstrated this by emulating a large cellular modem within 3,000× the speed of real life, a 3,000,000× speedup over analog simulations, and a 120× speedup over RTL simulations.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131078675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gang Wu, Tao Lin, Hsin-Ho Huang, C. Chu, P. Beerel
{"title":"Asynchronous circuit placement by Lagrangian relaxation","authors":"Gang Wu, Tao Lin, Hsin-Ho Huang, C. Chu, P. Beerel","doi":"10.1109/ICCAD.2014.7001420","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001420","url":null,"abstract":"Recent asynchronous VLSI circuit placement approach tries to leverage synchronous placement tools as much as possible by manual loop-breaking and creation of virtual clocks. However, this approach produces an exponential number of explicit timing constraints which is beyond the ability of synchronous placement tools to handle. Thus, synchronous placer can only produce suboptimal results. Also, it can be very costly in terms of runtime. This paper proposed a new placement approach for asynchronous VLSI circuits. We formulated the asynchronous timing-driven placement problem and transform this problem into a weighted wirelength minimization problem based on a Lagrangian relaxation framework. The problem can then be efficiently solved using any standard wirelength-driven placement engine that can handle net weights. We demonstrate our approach on QDI PCHB asynchronous circuit with a state-of-art quadratic placer. The experimental results show that our algorithm can effectively improve the asynchronous circuits performance at placement stage. In addition, the runtime of our algorithm is shown to be more scalable to large-scale circuits compared with the loop-breaking approach.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124349722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy","authors":"Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang","doi":"10.1109/ICCAD.2014.7001381","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001381","url":null,"abstract":"Routability has become a challenging issue with designs scaling down. Recently, global-routing-based routing congestion estimators (GRCEs) are widely used to detect the routability problems in the early VLSI design stages. To make GRCEs fast, using parallel routing approaches to speed up GRCEs is a promising direction. However, integrating existing parallel routing approaches into a GRCE may degrade the accuracy of the GRCE, because the routing kernel of the GRCE has to be modified such that its routing behavior changes. This paper presents a resource-level parallel approach (RPA) to accelerate GRCEs. RPA is easy to implement and has no need to change the routing kernels of GRCEs. Thus, GRCEs accelerated by RPA can keep its routing behavior and the estimation accuracy. Moreover, this paper presents an analytical method to quantify the estimation accuracy of a GRCE. Traditionally, the accuracy of a GRCE is manually measured by how they look like between the congestion maps generated by the GRCE and a real router, which may be inaccurate and time-consuming. In contrast, using the proposed quantifying method to evaluate the accuracy of a GRCE is more precise and faster.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116916828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A hierarchical approach for generating regular floorplans","authors":"Javier de San Pedro, J. Cortadella, Antoni Roca","doi":"10.1109/ICCAD.2014.7001422","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001422","url":null,"abstract":"The complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more reusable parts. In this work we introduce HiReg, a new floorplanning algorithm that generates regular floorplans. HiReg automatically extracts repeating patterns in a design by using graph mining techniques. Regularity is exploited by reusing the same floorplan for multiple instances of a pattern, as long as neither area, wire length or existing hierarchy constraints are violated or compromised. The proposed scheme is targeted towards early system-level design of chip multiprocessors (CMPs). Experiments show the scalability of the method for many-core CMPs and competitive results in area and wire length.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123514559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Planning and placing power clamps for effective CDM protection","authors":"Hsin-Chun Lin, Shih-Ying Liu, Hung-Ming Chen","doi":"10.1109/ICCAD.2014.7001423","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001423","url":null,"abstract":"The issue on reliability of the device becomes more critical as power density of device progressively increases with advancement of technology nodes. Smaller transistor and hence thinner gate oxide implies transistors are more vulnerable against an Electrostatic Discharge (ESD) event. Among the test models in ESD, Charged Device Model (CDM) has greater potential to cause catastrophic damage to the device due to its faster and larger discharging current. To protect against a CDM event, power clamps are placed across the design to offer a low resistance discharge path. However, conventional power clamp placement method to place power clamps generally relies on design experience. In this work, we propose a power clamp placement algorithm that places power clamp at strategic location which can effectively minimize number of power clamps while achieving better protection against a CDM event compared to conventional approach.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122765315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sheng-Wei Cheng, Yu-Fen Chang, Yuan-Hao Chang, H. Wei, W. Shih
{"title":"Warranty-aware page management for PCM-based embedded systems","authors":"Sheng-Wei Cheng, Yu-Fen Chang, Yuan-Hao Chang, H. Wei, W. Shih","doi":"10.1109/ICCAD.2014.7001433","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001433","url":null,"abstract":"The thriving growth in mobile consumer electronics makes energy efficiency in the embedded system design an important and recurring theme. Phase Change Memory (PCM) has shown its potential in replacing DRAM as the main memory option due to its (65%) reduced energy requirements. However, when considering the usage of PCM main memory, its write endurance becomes a critical issue, and wear leveling design is a common approach to resolve this issue. Even though the wear leveling design should stress operation efficiency and overhead reduction, existing wear leveling strategies designed for PCM main memory are usually dedicated to prolonging the lifetime of PCM. In this paper, we propose the perspective that, instead of valuing PCM lifetime exploitation as the first priority, we should turn to satisfy the product warranty period. To this end, further enhancement of operation efficiency and reduction of management overhead could be achieved. We thus propose a warranty-aware page management design to enhance the operation efficiency for managing the endurance issue in PCM. To show the effectiveness of the proposed design, we collected real traces on fiasco. OC by running SPEC2006 benchmarks with different write intensity workloads. The experiment results showed that our design reduced the overhead to one third of that of the state-of-the-art designs while still providing the same level of performance.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130303796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}