Planning and placing power clamps for effective CDM protection

Abstract

The issue on reliability of the device becomes more critical as power density of device progressively increases with advancement of technology nodes. Smaller transistor and hence thinner gate oxide implies transistors are more vulnerable against an Electrostatic Discharge (ESD) event. Among the test models in ESD, Charged Device Model (CDM) has greater potential to cause catastrophic damage to the device due to its faster and larger discharging current. To protect against a CDM event, power clamps are placed across the design to offer a low resistance discharge path. However, conventional power clamp placement method to place power clamps generally relies on design experience. In this work, we propose a power clamp placement algorithm that places power clamp at strategic location which can effectively minimize number of power clamps while achieving better protection against a CDM event compared to conventional approach.