2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)最新文献_第6页

Compaction-free compressed cache for high performance multi-core system 用于高性能多核系统的无压缩压缩缓存

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001344

Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang

引用次数: 2

A fast process variation and pattern fidelity aware mask optimization algorithm 一种快速的过程变化和模式保真度感知掩模优化算法

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001358

Ahmed Awad, A. Takahashi, S. Tanaka, C. Kodama

引用次数: 26

Toward scalable source level accuracy analysis for floating-point to fixed-point conversion 面向浮点到定点转换的可扩展源级精度分析

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001432

Gaël Deest, Tomofumi Yuki, O. Sentieys, Steven Derrien

引用次数: 9

Automated detection and verification of parity-protected memory elements 自动检测和验证奇偶保护的内存元素

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001322

E. Arbel, S. Koyfman, P. Kudva, Shiri Moran

{"title":"Automated detection and verification of parity-protected memory elements","authors":"E. Arbel, S. Koyfman, P. Kudva, Shiri Moran","doi":"10.1109/ICCAD.2014.7001322","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001322","url":null,"abstract":"With technology scaling and complexity, better error detection and correction mechanisms within chips and systems are becoming increasingly important in order to provide sufficient protection against both soft and hard errors. Verifying the correctness of error detection circuits and ensuring they provide enough design coverage is a hard problem which usually involves substantial amount of manual work. This problem is even more challenging in the presence of different design methodologies, such as with the inclusion of third party IP blocks where functional descriptions of logic designs may not be available. This paper addresses the problem by proposing a completely automated RTL-based verification flow for error detection and correction circuits. Several related challenges are solved: first, that of identification of potential error detection circuits in logic designs where no functional description or methodology hints are given. Second, identification of structures of the latches that are potentially protected by such error detection circuits. Third, using formal verification for ensuring that the implemented circuits for resiliency indeed detect all single bit errors in the latches they are intended to cover. The approach is described with parity detection as an example, although it is extensible to other coding methods such as ECC and state orthogonality checking. Novel algorithms are given and results on industrial designs are presented.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127649020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Generating multiple correlated probabilities for MUX-based stochastic computing architecture 基于mux的随机计算体系结构的多相关概率生成

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001400

Yili Ding, Yi Wu, Weikang Qian

引用次数: 8

Evolving physical design paradigms in the transition from 20/14 to 10nm process technology nodes 20/14制程技术节点向10奈米制程技术节点过渡过程中的物理设计范式演变

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001407

L. Capodieci

{"title":"Evolving physical design paradigms in the transition from 20/14 to 10nm process technology nodes","authors":"L. Capodieci","doi":"10.1109/ICCAD.2014.7001407","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001407","url":null,"abstract":"Advanced IC process technology nodes (28,20,14nm and below) have relied on the synergy of process-aware physical design and physical verification methodologies with design-aware yield engineering (on the manufacturing side), in order to fulfill ITRS scaling and performance requirements. These capabilities include not only additional design rules, or additional modeling capabilities, or incremental verification tools, but rather a qualitatively new set of DFM/DEM (Design For Manufacturing - Design Enabled Manufacturing) methodologies aimed at variability management, i.e. at characterization and remapping of systematic variability effects caused by design/process interaction. A typical example is a “correct by construction” router flow, augmented with yield detractor and yield enhancer patterns, implemented for 20nm high performance processor designs. In such a flow, timing (on the design side) and yield (on the manufacturing side) are co-optimized, in order to guarantee high yield and specified parametric performance in the first silicon run. In spite of current successes the incremental path down to 14nm will be disrupted, because of the hard physical limits simultaneously occurring in geometric scaling and electrical scaling, and the transition to 10 and 7 nm nodes will require a (re)volutionary DFM (Design For Manufacturing) paradigm. Building on the state-of-the-art in design/technology co-optimization this work will review the three most likely design/process scenarios for 10 and 7nm design enablement, which could potentially allow the synthesis of the “design gap” and “patterning gap” altogether.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127037355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient layout generation and evaluation of vertical channel devices 垂直通道设备的高效布局生成与评估

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001404

Wei-Che Wang, Puneet Gupta

{"title":"Efficient layout generation and evaluation of vertical channel devices","authors":"Wei-Che Wang, Puneet Gupta","doi":"10.1109/ICCAD.2014.7001404","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001404","url":null,"abstract":"Vertical gate-all-around (VGAA) has been shown to be one of the most promising devices for the scaling beyond 10nm for its reduced delay, large driving current, and good gate control. Moreover, emerging devices such as heterojunction tunneling FETs are more amenable to vertical fabrication. However, past studies of vertical channel devices focused more on regular memory architectures and simple standard cells like inverter. Since naive migration of regular FinFET layouts to vertical FETs yields little benefits, we identify several vertical efficient layout structures and propose novel layout generation heuristics for vertical channel devices. We also compare VGAA with symmetric and asymmetric source/drain architectures. The layout efficiencies of several VGAA structures, vertical double gate (VDG), lateral gate-all-around (LGAA), and FinFET are presented in our experiments. We observe that even though most vertical channel standard cells have more diffusion gaps than lateral cells do, they still benefit from vertical architectures in area because of the elimination of diffusion contacts. For asymmetric architectures, the area is larger than symmetric architectures because of the extra diffusion gaps needed, but our experiments indicate that for both symmetric and asymmetric architectures, vertical channel devices are likely to have a density advantage over lateral channel devices assuming that current drive strengths of both are similar.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130810944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Multi-level approximate logic synthesis under general error constraints 一般误差约束下的多级近似逻辑综合

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001398

Jin Miao, A. Gerstlauer, M. Orshansky

{"title":"Multi-level approximate logic synthesis under general error constraints","authors":"Jin Miao, A. Gerstlauer, M. Orshansky","doi":"10.1109/ICCAD.2014.7001398","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001398","url":null,"abstract":"We address the problem of multi-level approximate logic synthesis. Our strategy assumes existence of an optimized exact Boolean network, which is critical in practice since arithmetic blocks are rarely synthesized from 2-level representation automatically. The goal is to produce minimum cost circuits whose logic function deviates in a controlled manner from the exact function with deviations quantified by the magnitude and frequency of errors. We rely on network simplifications allowed by external don't cares (EXDCs). We formulate the error-magnitude constrained problem by using Boolean relations to capture the allowed error behavior in a more general manner compared to incompletely specified functions. Our key contribution is in finding sets of external don't cares that maximally approach the Boolean relation. The algorithm starts with an EXDC set that is overly relaxed and iteratively, and in a greedy fashion, identifies a feasible EXDC set by solving a series of conventional EXDC-based network optimizations. The algorithm then ensures compliance to error frequency constraints by recovering the correct outputs on the sought number of error-producing inputs while aiming to minimize the network cost increase. We applied the algorithm to several well-known adder and multiplier designs of varying bit-width. Even for small error magnitudes, the algorithm produces networks with gate count reduced by 30-50%, when the error frequency constraint is loose. This is up to 20% fewer gates than a naive EXDC-based approach.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129222280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 47

Hardware obfuscation using PUF-based logic 使用基于puf的逻辑进行硬件混淆

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001362

James Bradley Wendt, M. Potkonjak

引用次数: 72

Reinforcement learning based power management for hybrid electric vehicles 基于强化学习的混合动力汽车电源管理

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) Pub Date : 2014-11-03 DOI: 10.1109/ICCAD.2014.7001326

X. Lin, Yanzhi Wang, P. Bogdan, N. Chang, Massoud Pedram

{"title":"Reinforcement learning based power management for hybrid electric vehicles","authors":"X. Lin, Yanzhi Wang, P. Bogdan, N. Chang, Massoud Pedram","doi":"10.1109/ICCAD.2014.7001326","DOIUrl":"https://doi.org/10.1109/ICCAD.2014.7001326","url":null,"abstract":"Compared to conventional internal combustion engine (ICE) propelled vehicles, hybrid electric vehicles (HEVs) can achieve both higher fuel economy and lower pollution emissions. The HEV consists of a hybrid propulsion system containing one ICE and one or more electric motors (EMs). The use of both ICE and EM increases the complexity of HEV power management, and therefore requires advanced power management policies to achieve higher performance and lower fuel consumption. Towards this end, our work aims at minimizing the HEV fuel consumption over any driving cycle (without prior knowledge of the cycle) by using a reinforcement learning technique. This is in clear contrast to prior work, which requires deterministic or stochastic knowledge of the driving cycles. In addition, the proposed reinforcement learning technique enables us to (partially) avoid reliance on complex HEV modeling while coping with driver specific behaviors. To our knowledge, this is the first work that applies the reinforcement learning technique to the HEV power management problem. Simulation results over real-world and testing driving cycles demonstrate the proposed HEV power management policy can improve fuel economy by 42%.","PeriodicalId":426584,"journal":{"name":"2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 55