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ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)最新文献

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Design diagnosis using Boolean satisfiability 利用布尔可满足性进行设计诊断
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337569
Alexander Smith, A. Veneris, Anastasios Viglas
{"title":"Design diagnosis using Boolean satisfiability","authors":"Alexander Smith, A. Veneris, Anastasios Viglas","doi":"10.1109/ASPDAC.2004.1337569","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337569","url":null,"abstract":"Recent advances in Boolean satisfiability have made it an attractive engine for solving many digital VLSI design problems such as verification, model checking, optimization and test generation. Fault diagnosis and logic debugging have not been addressed by existing satisfiability-based solutions. We attempt to bridge this gap by proposing a satisfiability-based solution to these problems. The proposed formulation is intuitive and easy to implement. It shows that satisfiability captures significant problem characteristics and it offers different trade-offs. It also provides new opportunities for satisfiability-based diagnosis tools and diagnosis-specific satisfiability algorithms. Theory and experiments validate the claims and demonstrate its potential.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121769697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
Open architecture test system: not why but when! 开放架构测试系统:不是为什么，而是何时!
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337594
S. Chakradhar
{"title":"Open architecture test system: not why but when!","authors":"S. Chakradhar","doi":"10.1109/ASPDAC.2004.1337594","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337594","url":null,"abstract":"Due to rapidly escalating semiconductor manufacturing test costs, leading consumers (chip manufacturers) are urging the ATE industry to identify new test systems and business models that can significantly lower test costs. We examine the shifting consumer needs and identify attributes of a test system that can effectively meet the requirements of the consumer. Open test systems have the potential to reduce test costs, but they also result in seismic changes in the ATE industry. We discuss the effect of these changes on consumers, incumbent ATE vendors and new entrants. We conclude that benefits of open test systems are now visible within leading ATE vendors, but an industry-wide open test system is necessary to realize meaningful cost reductions for the semiconductor chip manufacturer.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications 集成了29Mb嵌入式DRAM的低功耗图形LSI，用于移动多媒体应用
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337635
Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, H. Yoo
{"title":"A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications","authors":"Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, H. Yoo","doi":"10.1109/ASPDAC.2004.1337635","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337635","url":null,"abstract":"A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, programmable power optimizer, and 29Mh embedded DRAM. Full 3D graphics pipeline featuring 264Mtexelds texture-mapped 3D graphics as well as 2D MPEG-4 video decoding can be realized while consuming less than 210mW and 12lmm2 chip area. The chip is implemented with 0.16μm pure DRAM process to reduce the fabrication cost. The real-time 3D graphics applications are successfully demonstrated by the fabricated chip on two PDA system boards.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131363208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Disjoint-support boolean decomposition combining functional and structural methods 结合功能和结构方法的不接合支持布尔分解
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337661
A. Martinelli, R. Krenz, E. Dubrova
{"title":"Disjoint-support boolean decomposition combining functional and structural methods","authors":"A. Martinelli, R. Krenz, E. Dubrova","doi":"10.1109/ASPDAC.2004.1337661","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337661","url":null,"abstract":"This paper presents an algorithm for disjointsupport decomposition of Boolean functions which combines functional and structural approaches. First, a set of proper cut points is identified in the circuit by using dominator relations (structural method). Then, the circuit is partitioned along these cut points and a BDD-based decomposition is applied to the resulting smaller functions (functional method). Previous work on Boolean decomposition used only single methods and did not integrate a combined strategy. The experimental results show that the presented technique is more robust than a pure BDD-based approach and produces better-quality decompositions.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128338453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process 数字CMOS工艺中环形振荡器VCO和LC振荡器时钟生成锁相环的性能比较
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337641
T. Miyazaki, M. Hashimoto, H. Onodera
{"title":"A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process","authors":"T. Miyazaki, M. Hashimoto, H. Onodera","doi":"10.1109/ASPDAC.2004.1337641","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337641","url":null,"abstract":"This paper dwcribes a performance comparison of two PLLs for clock generation using a ring oscillator based VCO and an LC oscillator based VCO. We fabricate two 1.6GHz PLLS in a 0.18 μm digital CMOS process and compare their performances baser! on the measurement results. We also prodiets major performances of PLLs in the futum such as jitter, power consumption and chip area, based on a qualitative evaluation in an analytic way.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130409878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method 三维互连电阻的快速准确提取:改进的准多介质加速边界元法
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337684
Xiren Wang, Deyan Liu, Wenjian Yu, Zeyi Wang
{"title":"Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method","authors":"Xiren Wang, Deyan Liu, Wenjian Yu, Zeyi Wang","doi":"10.1109/ASPDAC.2004.1337684","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337684","url":null,"abstract":"With the deep submicron process technology used widely, fast and accurate extraction of parasitic parameters hecomes very important for VLSI designs. In this paper, a fast and accurate method is presented for 3-D interconnect resistance extraction. This method is the boundary element method accelerated by the improved Quasi-Multiple Medium (QMM) algorithm. The improvement upon QMM includes the new strategy of cutting conductors un-averagely, only calculating conductors in current paths, dividing boundary elements only in one direction if possible and using linear elements for some straight conductors. Experiments on actual layout cases show that, compared with the famous Raphael, the proposed method has a speedup of hundreds while preserving higher accuracy.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130679661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SRAM delay fault modeling and test algorithm development SRAM延迟故障建模与测试算法开发
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337548
Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu
{"title":"SRAM delay fault modeling and test algorithm development","authors":"Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu","doi":"10.1109/ASPDAC.2004.1337548","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337548","url":null,"abstract":"With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. We present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k read/write operations, where N is the number of words and k is the word count in a row.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"33 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134244312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction 基于lut的无重复限制FPGA技术映射的面积最小算法
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337687
Chi-Chou Kao, Y. Lai
{"title":"Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction","authors":"Chi-Chou Kao, Y. Lai","doi":"10.1109/ASPDAC.2004.1337687","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337687","url":null,"abstract":"Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a polynomial time algorithm which can run in O(n3) time to generate an efficient solution where n is the total number of gates in the circuit. The proposed algorithm partitions the graph representing the given circuit into subgraphs such that the solution can be obtained by merging the subgraph solutions. The greedy technique is then used to find the solution for each subgraph. It is shown that except for some cases the greedy method can find an optimal solution of a given problem. We have tested our algorithm on a set of benchmark examples. The experimental results demonstrate the effectiveness of our algorithm.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134518212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A simplifiediyansmission-line based crosstalk noise model for on-chip RLC wiring 片上RLC布线中基于传输线的简化串扰噪声模型
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337715
K. Agarwal, D. Sylvester, D. Blaauw
{"title":"A simplifiediyansmission-line based crosstalk noise model for on-chip RLC wiring","authors":"K. Agarwal, D. Sylvester, D. Blaauw","doi":"10.1109/ASPDAC.2004.1337715","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337715","url":null,"abstract":"In this paper, we prerent B new RLC emstalk noise model Ihat combines simplicity, accuracy, and generality. The new model b based on transmission line theory and is applicable to asymmetric driver and line conliguratiions. The results show that the model captures both Ihe waveform shape and peak noise accurately (average emr in peak noise was 6.5%). A key feature of the new model is Ihat its derivation and form enables physical insight into Ihe dependency of total coupling noise on Itlevant physical design paramten. The model is applied to investigate Ihe impact of various physical design optimizations (e.g., wire sizing and sparing, shield insertion) on total RLC coupled noise. Results indicate that wmmon (capacitive) noise avoidance techniques can behave quite dilTerenUy when baIh capacitive and inductive coupling are convidered together.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130975269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Layer assignment for crosstalk risk minimization 为使相声风险最小化而进行的层分配
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337558
Di Wu, Jiang Hu, R. Mahapatra, Min Zhao
{"title":"Layer assignment for crosstalk risk minimization","authors":"Di Wu, Jiang Hu, R. Mahapatra, Min Zhao","doi":"10.1109/ASPDAC.2004.1337558","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337558","url":null,"abstract":"In ultra-deep submicron technology, crosstalk noise is so severe that crosstalk avoidance merely in detailed routing is not adequate and it has to be considered in earlier design stages. We propose two heuristics for crosstalk mitigation in layer assignment, which is a stage between global routing and detailed routing, so that subsequent crosstalk avoidance in detailed routing can be more attainable. The predetailed-routing crosstalk is estimated through a probabilistic model. The constraint on the amount of vias is also considered. Experimental results on benchmark circuits confirm the effectiveness of the proposed heuristics.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134329465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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