ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)最新文献_第6页

Low power design using dual threshold voltage 采用双阈值电压的低功耗设计

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337566

Yen-Te Ho, TingTing Hwang

引用次数: 35

Analog LSI for motion detection of approaching object with simple-shape recognition based on lower animal vision 基于低等动物视觉的简单形状识别的接近目标运动检测模拟LSI

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337633

K. Nishio, H. Yonezu, S. Sawa, Y. Furukawa

引用次数: 1

Performance-driven global placement via adaptive network characterization 通过自适应网络表征实现性能驱动的全局布局

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337554

M. Ekpanyapong, S. Lim

引用次数: 2

On handling arbitrary rectilinear shape constraint 关于任意直线形状约束的处理

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337536

Xiaoping Tang, Martin D. F. Wong

{"title":"On handling arbitrary rectilinear shape constraint","authors":"Xiaoping Tang, Martin D. F. Wong","doi":"10.1109/ASPDAC.2004.1337536","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337536","url":null,"abstract":"Nonrectangular (rectilinear) shape occurs very often in deep submicron floorplanning. Most previous algorithms are designed to handle only convex rectilinear blocks. However, handling concave rectilinear shape is necessary since a simple \"U\" shape is concave. A few works could address concave rectilinear block explicitly. In (K. Fujiyoshi, et al., (1999)), a necessary and sufficient condition of feasible sequence pair is proposed for arbitrary rectilinear shape in terms of constraint graph. However, no constraint is imposed on sequence pair representation itself. The search for feasible sequence pair mainly depends on the simulated annealing, which implies unnecessary inefficiency. In many cases, it takes very long time or even is unable to find the feasible placement. Furthermore, it takes O(n/sup 3/) runtime to evaluate each sequence pair, which leaves much space for improvement. We propose a new method to handle arbitrary rectilinear shape constraint based on sequence pair representation. We explore the topological property of feasible sequence pair, and use it to eliminate lots of infeasible sequence pairs, which implies speeding up the convergence of simulated annealing process. The evaluation of a sequence pair is based on longest common subsequence computation, and achieves significantly faster runtime (O(mnloglogn) time where m is the number of rectilinear-shape constraints, n is the number of rectangular blocks/subblocks). The algorithm can handle fixed-frame floorplanning and min-area floorplanning as well.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122537895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Analog circuit behavioral modeling via wavelet collocation method with auto-companding 基于自扩展小波配置法的模拟电路行为建模

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337538

Jian Wang, Jun Tao, Xuan Zeng, C. Chiang, Dian Zhou

引用次数: 4

Large-scale linear circuit simulation with an inversed inductance matrix 具有反电感矩阵的大规模线性电路仿真

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337628

C. Mizuta, J. Iwai, K. Machida, T. Kage, H. Masuda

引用次数: 6

A cosynthesis algorithm for application specific processors with heterogeneous datapaths 具有异构数据路径的应用程序特定处理器的协同合成算法

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337575

Yuichiro Miyaoka, N. Togawa, M. Yanagisawa, T. Ohtsuki

引用次数: 0

Exploiting state encoding for invariant generation in induction-based property checking 利用状态编码在基于归纳的属性检查中生成不变量

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337612

Markus Wedler, D. Stoffel, W. Kunz

引用次数: 8

Buffer allocation algorithm with consideration of routing congestion 考虑路由拥塞的缓冲区分配算法

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337666

Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu

引用次数: 2

Synthesizable HDL generation method for configurable VLIW processors 可配置VLIW处理器的可合成HDL生成方法

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337712

Yuki Kobayashi, Shinsuke Kobayashi, K. Okuda, K. Sakanushi, Y. Takeuchi, M. Imai

引用次数: 9