ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)最新文献_第10页

Accurate and eff icient flow based congestion estimation in floorplanning 准确有效的基于流量的楼层规划拥堵估计

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337677

Z. C. Shen, C. Chu

{"title":"Accurate and eff icient flow based congestion estimation in floorplanning","authors":"Z. C. Shen, C. Chu","doi":"10.1109/ASPDAC.2004.1337677","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337677","url":null,"abstract":"Congestion has been a topic of great importance in the floorplanning of deep-submicron Odesign. In this paper, we design an accurate and efficient congestion estimation model by performing global routing. We interpret the global routing problem as a flow problem of several commodities and relax the integral flow constraints. The objective of resulting fractional flow problem is to minimize the maximum congestion over all edges in the inner dual graph [ 131. The underlying routing graph for each commodity is derived by assigning directions to the inner dual graph edges. We design an efficient two-phase algorithm to solve this fractional flow problem. The first phase is denoted as Incoming Flow Balancing (IFB) by which a good initial solution is derived. The second phase is called Srepwise Flow Refinement (SFR) by which the maximum congestion of the solution in first phase is iteratively reduced to its optimal value. In addition, a valid global routing solution can be obtained by applying a simple rounding procedure on the fractional flow solution. The maximum congestion after rounding is only increased by 2.82% on average according to our experimental results. which justifies the use of fractional flow to estimate the routing congestion. Finally. we demonstrate our model by integrating it into a simulated annealing (SA) based floorplanner, where we use the maximum congestion as part of the cost of SA. The experimental results show that, on average, our congestion-driven floorplanner can generate a much less congested floorplan (-36.44%) with a slight sacrifice in area (+1.30%) and wirelength (+2.64%). The runtime of the whole SA process is only increased moderately (+270%).","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122779085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Efficient reachability checking using sequential SAT 使用顺序SAT进行有效的可达性检查

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337611

G. Parthasarathy, Madhu K. Iyer, K. Cheng, Li-C. Wang

引用次数: 8

An image-sensor-based optical receiver fabricated in a standard 0.35-/spl mu/m CMOS technology for free-space optical communications 一种基于图像传感器的光接收机，采用标准的0.35-/spl μ m CMOS技术制造，用于自由空间光通信

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337646

K. Kagawa, Tomoaki Kawakami, Hiroaki Asazu, T. Ikeuchi, A. Fujiuchi, J. Ohta, M. Nunoshita

引用次数: 0

Instruction buffering exploration for low energy VLIWs with instruction clusters 带指令簇的低能量VLIWs指令缓冲探索

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337708

T. Aa, M. Jayapala, F. Barat, Geert Deconinck, R. Lauwereins, F. Catthoor, H. Corporaal

引用次数: 23

Jitter spectral extraction for multi-gigahertz signal 多千兆赫信号的抖动频谱提取

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337584

C. Ong, Dongwoo Hong, K. Cheng, Li-C. Wang

引用次数: 24

A non-iterative model for switching window computation with crosstalk noise 含串扰噪声的开关窗计算的非迭代模型

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ISCAS.2004.1329317

O. Hafiz, Pinhong Chen, Janet Roveda

引用次数: 4

High-level area and power-up current estimation considering rich cell library 考虑丰富单元库的高电平面积和上电电流估计

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.5555/1015090.1015329

Fei Li, Lei He, J. Basile, Rakesh J. Patel, H. Ramamurthy

{"title":"High-level area and power-up current estimation considering rich cell library","authors":"Fei Li, Lei He, J. Basile, Rakesh J. Patel, H. Ramamurthy","doi":"10.5555/1015090.1015329","DOIUrl":"https://doi.org/10.5555/1015090.1015329","url":null,"abstract":"Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces large power-up current that may affect circuit reliability as well as introduce performance loss. We present an in-depth study of high-level power-up current modeling and estimation in the context of a full custom design environment with a rich cell library. We propose a methodology to estimate the circuit area in terms of gate count and maximum power-up current for any given logic function. We build novel estimation metrics based on logic synthesis and gate level analysis using only a small number of typical circuits, but no further logic synthesis and gate level analysis are needed during our estimation. Compared to time-consuming logic synthesis and gate level analysis, the average errors for circuits from a leading industrial design project are 23.59% for area and 21.44% for maximum power-up current. In contrast, estimation based on quick synthesis leads to llx area difference in gate count for an Bbit adder.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126155065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Improving simulation-based verification by means of formal methods 利用形式化方法改进基于仿真的验证

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337670

G. Fey, R. Drechsler

引用次数: 26

Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures 解码滤波器缓存节能指令缓存层次结构在超标量架构

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337602

K. Vivekanandarajah, T. Srikanthan, S. Bhattacharyya

{"title":"Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures","authors":"K. Vivekanandarajah, T. Srikanthan, S. Bhattacharyya","doi":"10.1109/ASPDAC.2004.1337602","DOIUrl":"https://doi.org/10.1109/ASPDAC.2004.1337602","url":null,"abstract":"The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily attributed to the high energy consumption of fetch and decode circuitry, pursuant to the high instruction issue rate required of these high performance processors. Predictive decode filter cache (DFC) has been shown to be effective in reducing the fetch and decode energy consumed by the instruction cache hierarchy of inorder single issue processors. We propose the architectural level enhancements to facilitate the incorporation of the DFC in wide issue superscalar processors for an energy efficient memory hierarchy. Extensive simulations on the modified superscalar architecture shows that the use of the (predictor based) DFC results in an average reduction of 17.33% and 25.09% fetch energy reduction in LI cache along with 37.2% and 46.6% reduction in number of decodes for 64 and 128 instruction DFC respectively. This fetch and decode energy savings are achieved with minimal reduction in the average instruction per cycle (IPC) of 0.54% and 0.73% for 64 and 128 instruction DFC for the selected set of spec2000 benchmarks.","PeriodicalId":426349,"journal":{"name":"ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130454383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A retinal prosthetic device using a pulse-frequency-modulation CMOS image sensor 一种采用脉冲频率调制CMOS图像传感器的视网膜假体装置

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI: 10.1109/ASPDAC.2004.1337643

J. Ohta, T. Furumiya, D. C. Ng, A. Uehara, K. Kagawa, T. Tokuda, M. Nunoshita

引用次数: 0