SRAM延迟故障建模与测试算法开发

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI:10.1109/ASPDAC.2004.1337548

Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu

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引用次数: 5

摘要

随着深亚微米VLSI技术的出现，SRAM电路的工作速度已经发展到一定的水平，SRAM的高速测试已经成为一个重要的问题。我们提出了SRAM的延迟故障模型，即影响SRAM电路访问时间的故障。我们还开发了检测这些故障的测试算法。本文提出的SRAM延迟故障测试算法的复杂度为3N + 2k读/写操作，其中N为每行的字数，k为每行的字数。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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SRAM delay fault modeling and test algorithm development

With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. We present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k read/write operations, where N is the number of words and k is the word count in a row.

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ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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