数字CMOS工艺中环形振荡器VCO和LC振荡器时钟生成锁相环的性能比较

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI:10.1109/ASPDAC.2004.1337641

T. Miyazaki, M. Hashimoto, H. Onodera

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引用次数: 45

摘要

本文描述了两种锁相环的性能比较，分别采用基于环形振荡器和基于LC振荡器的压控振荡器产生时钟。我们在0.18 μm数字CMOS工艺中制造了两个1.6GHz锁相环，并比较了它们的性能。关于测量结果。我们还预测了锁相环在未来的主要性能，如抖动，功耗和芯片面积，基于定性评估的分析方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process

This paper dwcribes a performance comparison of two PLLs for clock generation using a ring oscillator based VCO and an LC oscillator based VCO. We fabricate two 1.6GHz PLLS in a 0.18 μm digital CMOS process and compare their performances baser! on the measurement results. We also prodiets major performances of PLLs in the futum such as jitter, power consumption and chip area, based on a qualitative evaluation in an analytic way.

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ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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