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Proceedings of 14th VLSI Test Symposium最新文献

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Segment delay faults: a new fault model 段延迟故障:一种新的故障模型
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510832
Keerthi Heragu, J. Patel, V. Agrawal
{"title":"Segment delay faults: a new fault model","authors":"Keerthi Heragu, J. Patel, V. Agrawal","doi":"10.1109/VTEST.1996.510832","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510832","url":null,"abstract":"We propose a segment delay fault model to represent any general delay defect ranging from a spot defect to a distributed defect. The segment length, L, is a parameter that can be chosen based on available statistics about the types of manufacturing defects. Once L is chosen, the fault list contains all segments of length L and paths whose entire lengths are less than L. Both rising and falling transitions at the origin of segments are considered. Choosing segments of a small length can prevent an explosion of the number of faults considered. At the same time, a defect over a segment may be large enough to affect any path passing through it. We present an efficient algorithm to compute the number of segments of any possible length in a circuit. We define various classes of segment delay fault tests-robust, transition, and non-robust-that offer a trade-off between fault coverage and quality.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 114
Development of test programs in a virtual test environment 在虚拟测试环境中开发测试程序
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510842
M. Miegler, W. Wolz
{"title":"Development of test programs in a virtual test environment","authors":"M. Miegler, W. Wolz","doi":"10.1109/VTEST.1996.510842","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510842","url":null,"abstract":"An environment for the efficient development of quality-assured mixed-signal test programs is introduced. The new approach provides links between design and test engineers based on a standard test description language VTML (Virtual Test Modelling Language). The language provides standardized description models for test system resources which can be mapped as well to equivalent simulation models as to real world test system hardware. Methods are provided to check the data consistency of test programs and to validate test program behavior using simulation models.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121367597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Applying two-pattern tests using scan-mapping 使用扫描映射应用双模式测试
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510884
N. Touba, E. McCluskey
{"title":"Applying two-pattern tests using scan-mapping","authors":"N. Touba, E. McCluskey","doi":"10.1109/VTEST.1996.510884","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510884","url":null,"abstract":"This paper proposes a new technique, called scan-mapping, for applying two-pattern tests in a standard scan design environment. Scan-mapping is performed by shifting the first pattern (V/sub 1/) into the scan path and then using combinational mapping logic to generate the second pattern (V/sub 2/) in the next clock cycle. The mapping logic is placed in the scan path and avoids the performance degradation of using more complex scan elements to apply two-pattern tests. A procedure is described for synthesizing the mapping logic required to apply a set of two-pattern tests. Scan-mapping can be used in deterministic testing to apply two-pattern tests that can't be applied using scan-shifting or functional justification, and it can be used in built-in self-testing (BlST) to improve the fault coverage for delay faults. Experimental results indicate that, for deterministic testing, scan-mapping can reduce area overhead and test time compared with using complex scan elements; and for pseudo-random testing, scan-mapping can significantly improve the fault coverage using only a small amount of mapping logic.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126794666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Testing trees for multiple faults 针对多个故障测试树
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510891
Anastasios Vergis, Carlos Tobon
{"title":"Testing trees for multiple faults","authors":"Anastasios Vergis, Carlos Tobon","doi":"10.1109/VTEST.1996.510891","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510891","url":null,"abstract":"A \"well behaving\" property is defined for each line (in general a bundle of wires) connecting two combinational logic cells. This property can be easily taken into account in the design process of the circuit. It is shown that all tree-structured circuits of combinational logic cells are easily testable for multiple faults if each line is \"well behaving\". The size of the test set increases only linearly as the number of cells increases. It is also shown that if no line is well-behaving then only the trivial (exhaustive) test set exists for the circuit, which increases exponentially as the number of cells increases. If there are well-behaving as well as non-well-behaving lines in the circuit, then the size of the test set increases exponentially with the sizes of the non-well-behaving subtrees and linearly with the number of such subtrees.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131644793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new digital test approach for analog-to-digital converter testing 一种新的模数转换器测试方法
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510836
M. Ehsanian, B. Kaminska, Karim Arabi
{"title":"A new digital test approach for analog-to-digital converter testing","authors":"M. Ehsanian, B. Kaminska, Karim Arabi","doi":"10.1109/VTEST.1996.510836","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510836","url":null,"abstract":"A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminate the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using CMOS 1.5 /spl mu/m technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converter or high resolution pipelined analog-to-digital converter. The presented BIST shows satisfactory results for 9-bit pipelined analog-to-digital converter.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123085751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Improving the accuracy of diagnostics provided by fault dictionaries 提高故障字典提供的诊断的准确性
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510855
J. Sheppard, W. Simpson
{"title":"Improving the accuracy of diagnostics provided by fault dictionaries","authors":"J. Sheppard, W. Simpson","doi":"10.1109/VTEST.1996.510855","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510855","url":null,"abstract":"Using nearest neighbor classification with fault dictionaries to resolve inexact signature matches in digital circuit diagnosis is inadequate. Nearest neighbor focuses on the possible diagnoses rather than on the tests. Our alternative-the information flow model-focuses on test information in the fault dictionary to provide more accurate diagnostics.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115637617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design 减少DFT对模拟集成电路性能的影响:改进的sw运算放大器设计
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510833
D. Vázquez, J. Huertas, A. Rueda
{"title":"Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design","authors":"D. Vázquez, J. Huertas, A. Rueda","doi":"10.1109/VTEST.1996.510833","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510833","url":null,"abstract":"This paper focuses on the implementation of the 'sw-op amp' concept for analog circuits testing. Some alternative CMOS implementations are presented and compared in terms of influential parameters from a performance and cost point of view. Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"9 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121012468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Iterative test-point selection for analog circuits 模拟电路的迭代测试点选择
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510837
J. V. Spaandonk, T. Kevenaar
{"title":"Iterative test-point selection for analog circuits","authors":"J. V. Spaandonk, T. Kevenaar","doi":"10.1109/VTEST.1996.510837","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510837","url":null,"abstract":"A method is presented which is useful for functional testing of analog circuits. It selects a set of rest points from a large set of candidate test points by combining a well-known decomposition technique from linear algebra with an iterative algorithm. The influence of random measurement errors is taken into account. Examples demonstrate that the method allows the circuit behavior to be determined with high precision, even in the presence of large measurement errors.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126725704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Increasing testability by clock transformation (getting rid of those darn states) 通过时钟转换增加可测试性(摆脱那些恼人的状态)
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510861
K. Rajan, D. E. Long, M. Abramovici
{"title":"Increasing testability by clock transformation (getting rid of those darn states)","authors":"K. Rajan, D. E. Long, M. Abramovici","doi":"10.1109/VTEST.1996.510861","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510861","url":null,"abstract":"We provide a new answer to the fundamental question \"Why is sequential test generation so difficult?\" the presence of darn (Difficult And Really Needed) states. A darn state is both difficult to reach and required to detect some faults. We introduce a method for identifying darn stares, along with a technique to measure their detrimental effect on the fault coverage. Darn states are the result of detrimental correlation between flip-flops (FFs) sharing the same clock. We propose a novel DFT technique in which FFs are partitioned into different groups having independent clocks during resting. The goal of partitioning is to increase the fault coverage by transforming darn states into easy-to-reach states. The proposed DFT has small area overhead and no performance penalty.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127320007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A sampling technique for diagnostic fault simulation 诊断故障仿真的采样技术
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510857
S. Chakravarty
{"title":"A sampling technique for diagnostic fault simulation","authors":"S. Chakravarty","doi":"10.1109/VTEST.1996.510857","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510857","url":null,"abstract":"The quality of diagnostic test sets (DTS) are determined using diagnostic fault simulation (DFS). We propose a novel approximation algorithm, called \"EC/IC Sampling\", for DFS. It samples the set of equivalence classes (EC)/indistinguishable classes (IC). An approach to sample ECs/ICs implicitly, without explicitly enumerating the set of ECs/ICs, is presented. Experimental evaluation of the proposed technique show it to be very effective.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126443609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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