Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design

Abstract

This paper focuses on the implementation of the 'sw-op amp' concept for analog circuits testing. Some alternative CMOS implementations are presented and compared in terms of influential parameters from a performance and cost point of view. Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell.