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Proceedings of 14th VLSI Test Symposium最新文献

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Test response compaction using arithmetic functions 使用算术函数测试响应压缩
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510882
A. P. Stroele
{"title":"Test response compaction using arithmetic functions","authors":"A. P. Stroele","doi":"10.1109/VTEST.1996.510882","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510882","url":null,"abstract":"Configurations of registers and adders, subtracters, or arithmetic logic units, which are available in many data paths, can be utilized to generate test patterns and compact test responses. This paper analyzes aliasing in these configurations when the test responses of circuits with arbitrary combinational faults are compacted, and gives the limiting values that the aliasing probability tends to for increasing test lengths. Configurations that feed back the overflow during addition or the underflow during subtraction are the best choices. In some of them the probability of aliasing tends to a limiting value of 1/(2/sup k/-1), which is almost the same as in compactors based on linear feedback shift registers with irreducible characteristic polynomials.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116598659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Challenges in future technologies 未来技术的挑战
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510827
K. Eshraghian
{"title":"Challenges in future technologies","authors":"K. Eshraghian","doi":"10.1109/VTEST.1996.510827","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510827","url":null,"abstract":"The rapidly emerging area of Ultra High-Speed processing that underpins the transformation of new concepts into working systems necessitates for evolutionary changes in not only the technology base and the strategy for physical mapping of such systems, but also the all important issue of testability and testing. The systems that are mostly affected, and indeed in the next decade or so would require an ever increasing processing power, include real-time signal processors and image processors, computer vision, telecommunications, biomedical systems and personal interactive communicators having processing capability that far exceeds that of the present day super computers. Advances in conventional CMOS over the years have been based on device scaling. As submicron dimensions are approached, further scaling of CMOS becomes increasingly complex and fundamental limits will soon emerge. The emergence of the fifth generation of ICs will be characterized by complexities in excess of 10-20 million devices where integration of Photonics (control of photons) with that of Electronics (control of electrons), will provide the arena for creativity in this new design paradigm.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128905588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the effects of test compaction on defect coverage 测试压缩对缺陷覆盖率的影响
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510889
S. Reddy, I. Pomeranz, S. Kajihara
{"title":"On the effects of test compaction on defect coverage","authors":"S. Reddy, I. Pomeranz, S. Kajihara","doi":"10.1109/VTEST.1996.510889","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510889","url":null,"abstract":"We study the effects of test compaction on the defect coverage of test sets for modeled faults. Using a framework proposed earlier, defects are represented by surrogate faults. Within this framework, we show that the defect coverage does not have to be sacrificed by test compaction, if the test set is computed using appropriate test generation objectives. Moreover, two test sets, one compacted and one non-compacted, generated using the same test generation objectives, typically have similar defect coverages, even if the compacted one is significantly smaller than the uncompacted one. Test generation procedures and experimental results to support these claims are presented.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134020051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
Scan insertion criteria for low design impact 低设计影响的扫描插入标准
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510831
S. Barbagallo, Monica Lobetti Bodoni, D. Medina, Fulvio Corno, P. Prinetto, M. Reorda
{"title":"Scan insertion criteria for low design impact","authors":"S. Barbagallo, Monica Lobetti Bodoni, D. Medina, Fulvio Corno, P. Prinetto, M. Reorda","doi":"10.1109/VTEST.1996.510831","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510831","url":null,"abstract":"The paper focuses an the constraints that the new silicon technologies impose on the implementation of partial and full scan approach. In particular the ordering of Flip-Flops inside each scan chain must be decided taking into account the capacitance constraints imposed by new technologies. The main goal of this paper is to prove that recent technologies impose a new design flow, exploiting layout information for scan chain reordering. Two algorithms are then described, which reduce both the average and the maximum distance between FFs in the chains, thus reducing the power dissipation of the circuit, too. Preliminary results, obtained through the implementation of the algorithms in the Italtel Design Environment and their application on a sample circuit, are reported.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"84 3-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132186571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Current signatures [VLSI circuit testing] 电流特征[VLSI电路测试]
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510844
A. Gattiker, Wojciech Maly
{"title":"Current signatures [VLSI circuit testing]","authors":"A. Gattiker, Wojciech Maly","doi":"10.1109/VTEST.1996.510844","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510844","url":null,"abstract":"In this paper we demonstrate that performing I/sub DDQ/ testing against a single threshold current value does not make sense. In place of the single current threshold we propose the \"current signature\". A die's current signature takes into account the relative measured level of current on all applied I/sub DDQ/ vectors. Preliminary results of current signature applications are discussed as well.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130241798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 120
Design of a fast, easily testable ALU 设计一个快速，易于测试的ALU
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510829
R. D. Blanton, J. Hayes
{"title":"Design of a fast, easily testable ALU","authors":"R. D. Blanton, J. Hayes","doi":"10.1109/VTEST.1996.510829","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510829","url":null,"abstract":"The design and implementation of a fast, easily testable arithmetic-logic unit (ALU) is described. It is built around an adder design which is level-testable (L-testable), implying that the number of test patterns required to detect all functional faults in modules grows logarithmically with the size of the ALU. L-testability is achieved by exploiting some inherent properties of carry-lookahead addition. The resulting ALU design requires only two extra inputs, regardless of the size of the ALU. For an 8-bit implementation that has little impact on performance, the area overhead is shown to be less than 9%.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132837157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Standard and ROM-based synthesis of FSMs with control flow checking capabilities 具有控制流检查功能的fsm的标准和基于rom的综合
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510839
X. Wendling, R. Rochet, R. Leveugle
{"title":"Standard and ROM-based synthesis of FSMs with control flow checking capabilities","authors":"X. Wendling, R. Rochet, R. Leveugle","doi":"10.1109/VTEST.1996.510839","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510839","url":null,"abstract":"This paper deals with the detection of sequencing errors in finite state machines. Several control-flow checking methods, implemented in an automatic synthesis tool, are presented. The contribution of this paper lies in that these methods are introduced in the ROM-based architecture, and compared to equivalent methods available in the standard synthesis flow.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124986263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems 用于超可靠容错系统的并发自测试嵌入式检查器
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510848
E. Sogomonyan, M. Gössel
{"title":"Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems","authors":"E. Sogomonyan, M. Gössel","doi":"10.1109/VTEST.1996.510848","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510848","url":null,"abstract":"In this paper it is shown how a self-checking checker can be designed to monitor systems with very few encoded outputs which are code words of an arbitrary separable error detection code. The checker is completely tested in normal operation mode, independent of the number of code words which are to be monitored. If an error has been indicated in normal operation mode the erroneous component of the system can be identified in test mode by the same hardware. A linear feedback shift register (LFSR) is included between the information bits of the outputs of the monitored systems and the inputs of the check-bit generator. A corrector (Cor) adjusts the check bits of the monitored system. The general systematic design method given in this paper is applied to parity codes, duplication codes, arithmetic codes and Berger codes. The approach is useful for the design of ultra-reliable fault-tolerant systems, especially for monitoring systems with very few outputs in normal operation mode.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125009202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design of a fault tolerant 100 Gbits solid-state mass memory for satellites 卫星100gbits固态大容量容错存储器的设计
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510869
M. Kluth, François Simon, J. Gall, E. Müller
{"title":"Design of a fault tolerant 100 Gbits solid-state mass memory for satellites","authors":"M. Kluth, François Simon, J. Gall, E. Müller","doi":"10.1109/VTEST.1996.510869","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510869","url":null,"abstract":"This paper summarizes the studies conducted by Alcatel Espace and Alcatel Alsthom Recherche to design a new generation of fault tolerant 100 Gbits mass memories for satellites, based on VLSI components. In the context of space applications, stringent dependability constraints have to be met and fault tolerance is a design objective. To reach this tolerance mechanisms including error detection and tests are needed.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127816568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An approach for testing programmable/configurable field programmable gate arrays 一种测试可编程/可配置现场可编程门阵列的方法
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510892
Wei-Kang Huang, F. Lombardi
{"title":"An approach for testing programmable/configurable field programmable gate arrays","authors":"Wei-Kang Huang, F. Lombardi","doi":"10.1109/VTEST.1996.510892","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510892","url":null,"abstract":"This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics. A hybrid fault model is introduced based on a physical and behavioral characterization; this permits the detection of a single fault, as either a stuck-at or a functional fault. A general approach which regards testing as can application for the reconfigurable FPGA, is then proposed. It is shown that different arrangements of disjoint one-dimensional arrays with unilateral horizontal connections and common vertical input lines provide a very good solution. A further feature that is considered for array testing, is the relation between the configuration of the logic blocks and the number of I/O pins in the chip. As an example, the proposed approach is applied for testing the Xilinz 4000 family of FPGAs.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123072855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 114
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