{"title":"Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)","authors":"C. Stroud, S. Konala, Ping Chen, M. Abramovici","doi":"10.1109/VTEST.1996.510883","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510883","url":null,"abstract":"We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130374666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An unexpected factor in testing for CMOS opens: the die surface","authors":"H. Konuk, F. Ferguson","doi":"10.1109/VTEST.1996.510888","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510888","url":null,"abstract":"We present the experimental evidence, for the first time, that the die surface can act as an RC interconnect, becoming an important factor in determining the voltage of a floating wire created by a CMOS open. We present a circuit model for this effect verified with HSPICE simulations. A detailed analysis of potential mechanisms behind this phenomenon is provided. We also present our measurement results for the trapped charge deposited on floating gates during fabrication.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133917142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
