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Proceedings of 14th VLSI Test Symposium最新文献

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Safety computations in integrated circuits 集成电路中的安全计算
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510853
JeawLouis Dufour
{"title":"Safety computations in integrated circuits","authors":"JeawLouis Dufour","doi":"10.1109/VTEST.1996.510853","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510853","url":null,"abstract":"In order to ensure the safety of software-based railway control systems, MATRA TRANSPORT has developed at the beginning of the eighties an \"informational redundancy\" technique associating arithmetic coding and signature checking, with the adequate environment interfaces (generally fail-safe devices). Compared to traditional redundancy, the \"coded processor\" has the advantage of a rigorous mathematical safety demonstration, independent of the reliability of the underlying hardware, but there is an important cost to pay in terms of execution speed. One of the (strongly) desired evolutions of our systems is to have a unique centralized wayside equipment, the immediate corollary being the decentralization of inputs/outputs. In order to reach this goal, a new generation has been designed, replacing the software code calculations and the discrete numeric components used in coded input acquisition/coded output command by ASICs. Our experience shows that it is possible to perform safe computations in an ASIC, and even that in some cases ASICs are more adaptable to the safety constraints than software computations.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130867423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On estimating bounds of the quiescent current for I/sub DDQ/ testing I/sub DDQ/测试中静态电流边界的估计
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510843
A. Ferré, J. Figueras
{"title":"On estimating bounds of the quiescent current for I/sub DDQ/ testing","authors":"A. Ferré, J. Figueras","doi":"10.1109/VTEST.1996.510843","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510843","url":null,"abstract":"The quiescent current (I/sub DDQ/) consumed by an IC is a good indicator of the presence of a large of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ sensing circuitry. In this work, we present a method to estimate the non-defective I/sub DDQ/ consumption based on a hierarchical approach using layout (device), electrical (cell) and logic (circuit) information. The maximum of the defect-free I/sub DDQ/ is obtained with a technique based on ATPG. The results show that the proposed method gives the maximum defect-free I/sub DDQ/ for small circuits. For large circuits, heuristics to find lower and upper bounds of the maximum defect-free I/sub DDQ/ are presented. Uncertainty margins lower than 15% have been found in the circuits experimented on.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129279405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Analog circuit simulation and troubleshooting with FLAMES 模拟电路仿真和故障排除火焰
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510899
F. Mohamed, M. Manzouki, Anton Biasizzo, F. Novak
{"title":"Analog circuit simulation and troubleshooting with FLAMES","authors":"F. Mohamed, M. Manzouki, Anton Biasizzo, F. Novak","doi":"10.1109/VTEST.1996.510899","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510899","url":null,"abstract":"A new approach for analog circuit simulation and troubleshooting, based on the fuzzy logic paradigm, is presented in this paper. This approach allows to deal with soft faults, single or multiple ones, and with both impreciseness and uncertainty of information. It has been implemented in a system named FLAMES (Fuzzy Logic ATMS and Model-based Expert System), of which details are provided, together with different experimental results, for both simulation and troubleshooting processes.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126392316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and performance of CMOS TSPC cells for high speed pseudo random testing 高速伪随机测试用CMOS TSPC电池的设计与性能
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510880
Mohamed Soufi, Steve Rochon, Y. Savaria, B. Kaminska
{"title":"Design and performance of CMOS TSPC cells for high speed pseudo random testing","authors":"Mohamed Soufi, Steve Rochon, Y. Savaria, B. Kaminska","doi":"10.1109/VTEST.1996.510880","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510880","url":null,"abstract":"In this paper the problem of testing high speed CMOS circuits is considered. A test methodology based on a Built-in Self-Test scheme adapted to TSPC circuits is proposed. We show through HSpice simulations on netlists extracted from layout that this scheme can operate at more than 580 MHz. Moreover, an efficient solution to the problem of redesigning an easily testable functionally equivalent logic block to eliminate hard to test and untestable faults in TSPC circuits is introduced.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122422896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A diagnosability metric for parametric path delay faults 参数路径延迟故障的可诊断性度量
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510874
M. Sivaraman, A. Strojwas
{"title":"A diagnosability metric for parametric path delay faults","authors":"M. Sivaraman, A. Strojwas","doi":"10.1109/VTEST.1996.510874","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510874","url":null,"abstract":"Published research on delay fault testing has largely focused on generating a minimal set of test vector pairs to detect as many delay faults in a circuit as possible. Little regard has been paid to the diagnosability of delay faults in the quest for generating tests which can simultaneously detect a delay fault on many paths, one loses the ability to determine which paths caused a chip failure. In an earlier work [1996] we presented a framework to detect which paths are likely to have caused a chip failure for a set of delay fault tests, and to find the associated likely fabrication process parameter variations. Here, we quantify the diagnosability of a path delay fault for a test, and develop a methodology based on the diagnosis framework presented earlier to determine the diagnosability of each path delay fault detected by a given test set. Furthermore, we apply this approach to find the diagnosability of robust path delay faults for the ISCAS'89 benchmark circuits.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133448917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Full fault dictionary storage based on labeled tree encoding 基于标记树编码的全故障字典存储
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510854
V. Boppana, I. Hartanto, W. Fuchs
{"title":"Full fault dictionary storage based on labeled tree encoding","authors":"V. Boppana, I. Hartanto, W. Fuchs","doi":"10.1109/VTEST.1996.510854","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510854","url":null,"abstract":"The process of fault dictionary compaction can lead to a loss of information that is potentially useful in locating unmodeled failures. The focus of this paper is on developing alternative storage structures that can efficiently represent full fault dictionaries without discarding any information. We present the problem of storing the full fault dictionary storage as a labeled tree encoding problem. Two labeled trees are introduced to represent the diagnostic experiment. For the first tree, the unlabeled tree is stored using a binary string code, while the second tree is constructed so that the unlabeled tree is regular in structure, thus allowing implicit storage. Eight alternative representations based on the three label components are presented and two existing full fault dictionary representations (the matrix and the list dictionaries) are shown to be special cases in our general framework. Experimental results on the ISCAS 85 and ISCAS 89 circuits are used to study and characterize the performance of the proposed storage structures.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131929479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
A self-checking ALU design with efficient codes 一种具有高效代码的自检ALU设计
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510851
S. Gorshe, B. Bose
{"title":"A self-checking ALU design with efficient codes","authors":"S. Gorshe, B. Bose","doi":"10.1109/VTEST.1996.510851","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510851","url":null,"abstract":"Recently, a self-testing ALU design has been proposed that uses Berger codes and compares the check value of the ALU output to a predicted check value that is calculated based on the input operand check values. Berger codes have the property of being able to detect all unidirectional errors. More efficient codes exist for detecting up to t unidirectional errors. This paper examines applying these codes to self-testing ALU designs and shows that the potential savings in check circuitry over Berger codes is up to 61%, depending on the code and the information word length.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132347046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
On minimizing the number of test points needed to achieve complete robust path delay fault testability 最小化所需的测试点数量，以实现完整的鲁棒路径延迟故障可测性
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510870
Prasanti Uppaluri, U. Sparmann, I. Pomeranz
{"title":"On minimizing the number of test points needed to achieve complete robust path delay fault testability","authors":"Prasanti Uppaluri, U. Sparmann, I. Pomeranz","doi":"10.1109/VTEST.1996.510870","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510870","url":null,"abstract":"Recently, Pomeranz and Reddy (1994), presented a test point insertion method to improve path delay fault testability in large combinational circuits. A test application scheme was developed that allows test points to be utilized as primary inputs and primary outputs during testing. The placement of test points was guided by the number of paths and was aimed at reducing this number. Indirectly, this approach achieved complete robust path delay fault testability in very low computation times. In this paper, we use their test application scheme, however, we use more exact measures for guiding test point insertion like test generation and RD fault identification. Thus, we reduce the number of test points needed to achieve complete testability by ensuring that test points are inserted only on paths associated with path delay faults that are necessary to be tested and that are not robustly testable. Experimental results show that an average reduction of about 70% in the number of test points over the approach of Pomeranz and Reddy can be obtained.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114864269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring 通过I/sub DDQ/监控提高奇偶预测数组运算符的真实故障安全性
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510846
S. Manich, M. Nicolaidis, J. Figueras
{"title":"Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring","authors":"S. Manich, M. Nicolaidis, J. Figueras","doi":"10.1109/VTEST.1996.510846","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510846","url":null,"abstract":"Parity prediction arithmetic operator schemes have been widely studied in the past. Recently, it has been demonstrated that this prediction scheme can achieve Fault-Secureness in arithmetic circuits for stuck-at and stuck-open faults. In this paper it is shown that the detection capability improves if a current monitoring technique is used in conjunction with the parity prediction scheme. With this scheme the fault-secure property extends to bridging faults. The technique is validated by the topological design and SPICE simulation of a multiplier circuit.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122546306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the diagnosis of programmable interconnect systems: Theory and application 可编程互联系统的诊断:理论与应用
Proceedings of 14th VLSI Test Symposium Pub Date : 1996-04-28 DOI: 10.1109/VTEST.1996.510859
Wei-Kang Huang, Xiao-Tao Chen, F. Lombardi
{"title":"On the diagnosis of programmable interconnect systems: Theory and application","authors":"Wei-Kang Huang, Xiao-Tao Chen, F. Lombardi","doi":"10.1109/VTEST.1996.510859","DOIUrl":"https://doi.org/10.1109/VTEST.1996.510859","url":null,"abstract":"This paper considers the diagnosis of field programmable interconnect systems (FPIS) in which programmable grids made of switches are included. For this type of interconnects, the number of times the grid must be programmed and the programming sequence of the switches an two of the most important figures of merit for full diagnosis (defection and location with no aliasing and confounding). A hierarchical approach to diagnosis is proposed and fully characterized. The application of this technique to commercially available FPIS such as FPGAs, is discussed. It is shown that the proposed diagnostic technique can be applied to the general purpose interconnect of the FPGAs in the 3000 family by Xilinx.","PeriodicalId":424579,"journal":{"name":"Proceedings of 14th VLSI Test Symposium","volume":"18 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125766470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
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