On estimating bounds of the quiescent current for I/sub DDQ/ testing

Abstract

The quiescent current (I/sub DDQ/) consumed by an IC is a good indicator of the presence of a large of defects. However, the effectiveness of I/sub DDQ/ testing requires appropriate discriminability of defective and defect-free currents and hence it becomes necessary to estimate the currents involved in order to design the I/sub DDQ/ sensing circuitry. In this work, we present a method to estimate the non-defective I/sub DDQ/ consumption based on a hierarchical approach using layout (device), electrical (cell) and logic (circuit) information. The maximum of the defect-free I/sub DDQ/ is obtained with a technique based on ATPG. The results show that the proposed method gives the maximum defect-free I/sub DDQ/ for small circuits. For large circuits, heuristics to find lower and upper bounds of the maximum defect-free I/sub DDQ/ are presented. Uncertainty margins lower than 15% have been found in the circuits experimented on.