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Proceedings 1997 IEEE Multi-Chip Module Conference最新文献

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Intrinsic area array ICs: what, why, and how 内禀面积阵列ic:什么，为什么，以及如何
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569355
P. Dehkordi, C. Tan, D. Bouldin
{"title":"Intrinsic area array ICs: what, why, and how","authors":"P. Dehkordi, C. Tan, D. Bouldin","doi":"10.1109/MCMC.1997.569355","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569355","url":null,"abstract":"Area-array bonding technology (i.e. flip-chip, C4) was pioneered by IBM in the late 1960's as an alternative to periphery bonding technology (i.e. wire-bond). In recent years, several commercial companies have started offering bumping and flip-chip services. Flip-chip technology is expected to grow at at compound annual growth rate of 38% through the year 2001. The purpose of this paper is to address the IC design issues and alternatives that are presently being used for area-array bonding technology and show the impact of these design issues at the system level.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131205594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Strategies and structures for test access in mixed-signal MCMs 混合信号mcm测试接入策略与结构
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569360
M. Katoozi, H. Kutz, M. Soma, S. Huynh
{"title":"Strategies and structures for test access in mixed-signal MCMs","authors":"M. Katoozi, H. Kutz, M. Soma, S. Huynh","doi":"10.1109/MCMC.1997.569360","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569360","url":null,"abstract":"This paper describes a framework of strategies and structures to provide test access to mixed analog-digital MCMs. Recognizing that these mixed-signal devices contain a wide variety of components (from passive to active, from ASICs to off-the-shelf parts), the strategies presented include hierarchies of test access, and circuits to implement them. Frequently used structures such as the classical multiplexers and IEEE Std. 1149.1 are integrated with new structures more suitable for analog and mixed-signal test, such as current-based analog scan and IEEE P1149.4. Five general access circuit types and four major control topologies are described taking into account the requirements for test accuracy and the tradeoffs involved in design and test.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High Q inductors for MCM-Si technology 用于MCM-Si技术的高Q电感器
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569342
N. Klemmer, J. Hartung
{"title":"High Q inductors for MCM-Si technology","authors":"N. Klemmer, J. Hartung","doi":"10.1109/MCMC.1997.569342","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569342","url":null,"abstract":"Spiral inductors for microwave applications have been integrated on a silicon substrate in Multi Chip Module (MCM) technology. The fabricated inductors exhibit quality factors of up to 23. To the authors knowledge, these are the highest values for inductors on silicon reported so far. A software tool has been developed for fast and accurate design of planar spiral inductors.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130758844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Wire length and width bound generation for high-speed MCM and PCB designs 用于高速MCM和PCB设计的导线长度和宽度绑定生成
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569346
Haizhou Chen, E. Shragowitz, Jaebum Lee
{"title":"Wire length and width bound generation for high-speed MCM and PCB designs","authors":"Haizhou Chen, E. Shragowitz, Jaebum Lee","doi":"10.1109/MCMC.1997.569346","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569346","url":null,"abstract":"In this paper a methodology for computation of bounds on MCM and PCB net length and width consistent with timing and noise constraints is proposed. In this method. The initial length and width of each net are used for the AWE-based simulation. For the simulated length and width of the line, the delay and overshoot at receivers are expanded in the form of multi-variable Taylor series of length/width of segments for a multi-pin net. When the resulting linear delay and overshoot functions are bounded by timing and overshoot constraints, the line length and width that satisfy the constraints are obtained by solving a linear programming problem. Computed bounds can be used in practical design to reduce the number of timing and signal integrity violations and shorten the design cycle.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of an MCM FFT processor MCM FFT处理器的设计
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569349
R. Rozier, F. Kiamilev
{"title":"Design of an MCM FFT processor","authors":"R. Rozier, F. Kiamilev","doi":"10.1109/MCMC.1997.569349","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569349","url":null,"abstract":"We present the design of a parallel high-speed chipset for computing an 8,192-point (or less) 1-D complex fast Fourier transform (FFT). The chipset is composed of two chips-an FFT processing engine (FFTP) with on-chip twiddle factor generation and a random-access data storage element (FFTRAM). This chipset can be efficiently connected on an MCM to form a high-performance FFT calculation system.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131667230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
S parameter-based experimental modeling of high Q MCM inductor with exponential gradient learning algorithm 基于S参数的高Q MCM电感的指数梯度学习实验建模
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569353
Jinsong Zhao, W. Dai, R. Frye, K. Tai
{"title":"S parameter-based experimental modeling of high Q MCM inductor with exponential gradient learning algorithm","authors":"Jinsong Zhao, W. Dai, R. Frye, K. Tai","doi":"10.1109/MCMC.1997.569353","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569353","url":null,"abstract":"Lumped inductors are very desirable passive components in wireless/RF circuits integrated on MCM substrate. This paper models the inductor from on-wafer high frequency measurement by utilizing the S parameter formulation and exponential gradient method. The S parameter formulation enables us to understand the phase shifting effects within the model while the exponential gradient learning algorithm provides us with a more robust and better fitting technique than the gradient descent algorithm. Both the magnitudes and phases of all S parameters fit well for all the inductors we constructed. It is shown that the phase shifting of the distributed effects should not be neglected even in MCM-D technology. The resulting experimental model provides measurement-verified solid ground for circuit design and numerical characterization.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123926083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Low cost test of MCMs using testable die carriers 使用可测试的芯片载体进行mcm的低成本测试
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569359
K. Sasidhar, A. Chatterjee, M. Tswaminathan
{"title":"Low cost test of MCMs using testable die carriers","authors":"K. Sasidhar, A. Chatterjee, M. Tswaminathan","doi":"10.1109/MCMC.1997.569359","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569359","url":null,"abstract":"This paper addresses the issue of low cost testing of Multi Chip Modules (MCMs). The test cost of MCMs can be as much as 40 percent of the total cost of MCMs. Towards reducing the related assembly and test costs, we propose to use Testable Die Carriers (TDCs) to provide a unique solution for adding testability features to MCMs. Each TDC is a silicon logic device, containing embedded circuitry, which supports a single bare die. This eliminates the need for building expensive MCM testers as well as allows the use of a structured test methodology. The carrier contains Built In Self Test (BIST) and Boundary Scan (BS) architectures to test the die. Test algorithms are incorporated in the die carrier for enabling efficient interconnect and functional test of the die and the MCM.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114672392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigations on novel coaxial transmission line structures on MCM-L MCM-L上新型同轴传输线结构研究
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569343
A. Thiel, C. Habiger, G. Troster
{"title":"Investigations on novel coaxial transmission line structures on MCM-L","authors":"A. Thiel, C. Habiger, G. Troster","doi":"10.1109/MCMC.1997.569343","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569343","url":null,"abstract":"This paper presents recent investigations on a novel transmission line structure with improved RF-performance and increased shielding capability based on MCM-L interconnect technology. Three key issues are addressed: Maximization of usable interconnect bandwidth, reproducibility of the characteristic electrical properties in large-volume production, and minimization of inter-signal and electromagnetic interference. Thanks to recent improvements of MCM-L technology this new structure is processable in a cost-effective roll-to-roll production cycle. The electrical properties of the new structure are deduced from the well-known coaxial and triplate transmission line models. Furthermore, FEM-simulation results provide an estimation of the limitations of the proposed structure, which are caused by conductor and dielectric losses. The design of a test-vehicle intended for verification of the simulation results is presented. And finally, measurement results obtained from TDR/TDT and VNA measurement setups are reported and compared to the theoretical estimations.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127024248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CAD tools for area-distributed I/O pad packaging 用于区域分布式I/O封装的CAD工具
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569356
R. Farbarik, Xiaowen Liu, M. Rossman, P. Parakh, T. Basso, R. Brown
{"title":"CAD tools for area-distributed I/O pad packaging","authors":"R. Farbarik, Xiaowen Liu, M. Rossman, P. Parakh, T. Basso, R. Brown","doi":"10.1109/MCMC.1997.569356","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569356","url":null,"abstract":"The use of area interconnect packaging in high frequency microprocessors is motivated by its high-bandwidth and good power distribution capability. An MCM packaging scheme based on area-distributed I/O pads serves as the foundation of the PUMA project at the University of Michigan. Area interconnect facilitates high I/O counts, shorter interconnect routes, smaller power rails, and better thermal conductivity, all of which are important in high clock-rate digital systems. This paper introduces recently developed CAD tools that aid in the design of flip-chip area-interconnected integrated circuits. The tools permit the designer to place and route area bond pads as dictated by the layout of the microprocessor. System level issues, such as adequate power distribution and placement of area pad buffers, are addressed. The CAD system includes area pad power analysis, floorplanning, and routing tools.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117208297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
The impact of miniaturization and passive component integration in emerging MCM applications 小型化和无源元件集成对新兴MCM应用的影响
Proceedings 1997 IEEE Multi-Chip Module Conference Pub Date : 1997-02-04 DOI: 10.1109/MCMC.1997.569341
Y. Low, R. Frye
{"title":"The impact of miniaturization and passive component integration in emerging MCM applications","authors":"Y. Low, R. Frye","doi":"10.1109/MCMC.1997.569341","DOIUrl":"https://doi.org/10.1109/MCMC.1997.569341","url":null,"abstract":"We have designed multichip modules using three alternative technologies for a variety of applications, and have used the results to study the impact of miniaturization and passive component integration on module size, distribution of net length and estimated cost. We have chosen representative applications that include: a digital application with dense interconnections, a mixed-signal application for low-end portable electronics and an analog application requiring a large number of passive components. We compare conventional, laminate-based MCM technology with advanced thin-film-on-laminate technology and silicon-based thin-film MCM technology. We find that the advanced highly miniaturized technologies result not only in higher packaging density and shorter average net length, but in lower estimated module cost as well. Passive component integration can also lower module cost especially in mixed-signal and analog applications.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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