{"title":"混合信号mcm测试接入策略与结构","authors":"M. Katoozi, H. Kutz, M. Soma, S. Huynh","doi":"10.1109/MCMC.1997.569360","DOIUrl":null,"url":null,"abstract":"This paper describes a framework of strategies and structures to provide test access to mixed analog-digital MCMs. Recognizing that these mixed-signal devices contain a wide variety of components (from passive to active, from ASICs to off-the-shelf parts), the strategies presented include hierarchies of test access, and circuits to implement them. Frequently used structures such as the classical multiplexers and IEEE Std. 1149.1 are integrated with new structures more suitable for analog and mixed-signal test, such as current-based analog scan and IEEE P1149.4. Five general access circuit types and four major control topologies are described taking into account the requirements for test accuracy and the tradeoffs involved in design and test.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"194 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Strategies and structures for test access in mixed-signal MCMs\",\"authors\":\"M. Katoozi, H. Kutz, M. Soma, S. Huynh\",\"doi\":\"10.1109/MCMC.1997.569360\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a framework of strategies and structures to provide test access to mixed analog-digital MCMs. Recognizing that these mixed-signal devices contain a wide variety of components (from passive to active, from ASICs to off-the-shelf parts), the strategies presented include hierarchies of test access, and circuits to implement them. Frequently used structures such as the classical multiplexers and IEEE Std. 1149.1 are integrated with new structures more suitable for analog and mixed-signal test, such as current-based analog scan and IEEE P1149.4. Five general access circuit types and four major control topologies are described taking into account the requirements for test accuracy and the tradeoffs involved in design and test.\",\"PeriodicalId\":412444,\"journal\":{\"name\":\"Proceedings 1997 IEEE Multi-Chip Module Conference\",\"volume\":\"194 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-02-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1997 IEEE Multi-Chip Module Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1997.569360\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1997 IEEE Multi-Chip Module Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1997.569360","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Strategies and structures for test access in mixed-signal MCMs
This paper describes a framework of strategies and structures to provide test access to mixed analog-digital MCMs. Recognizing that these mixed-signal devices contain a wide variety of components (from passive to active, from ASICs to off-the-shelf parts), the strategies presented include hierarchies of test access, and circuits to implement them. Frequently used structures such as the classical multiplexers and IEEE Std. 1149.1 are integrated with new structures more suitable for analog and mixed-signal test, such as current-based analog scan and IEEE P1149.4. Five general access circuit types and four major control topologies are described taking into account the requirements for test accuracy and the tradeoffs involved in design and test.