{"title":"MCM FFT处理器的设计","authors":"R. Rozier, F. Kiamilev","doi":"10.1109/MCMC.1997.569349","DOIUrl":null,"url":null,"abstract":"We present the design of a parallel high-speed chipset for computing an 8,192-point (or less) 1-D complex fast Fourier transform (FFT). The chipset is composed of two chips-an FFT processing engine (FFTP) with on-chip twiddle factor generation and a random-access data storage element (FFTRAM). This chipset can be efficiently connected on an MCM to form a high-performance FFT calculation system.","PeriodicalId":412444,"journal":{"name":"Proceedings 1997 IEEE Multi-Chip Module Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of an MCM FFT processor\",\"authors\":\"R. Rozier, F. Kiamilev\",\"doi\":\"10.1109/MCMC.1997.569349\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present the design of a parallel high-speed chipset for computing an 8,192-point (or less) 1-D complex fast Fourier transform (FFT). The chipset is composed of two chips-an FFT processing engine (FFTP) with on-chip twiddle factor generation and a random-access data storage element (FFTRAM). This chipset can be efficiently connected on an MCM to form a high-performance FFT calculation system.\",\"PeriodicalId\":412444,\"journal\":{\"name\":\"Proceedings 1997 IEEE Multi-Chip Module Conference\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-02-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1997 IEEE Multi-Chip Module Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1997.569349\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1997 IEEE Multi-Chip Module Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1997.569349","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present the design of a parallel high-speed chipset for computing an 8,192-point (or less) 1-D complex fast Fourier transform (FFT). The chipset is composed of two chips-an FFT processing engine (FFTP) with on-chip twiddle factor generation and a random-access data storage element (FFTRAM). This chipset can be efficiently connected on an MCM to form a high-performance FFT calculation system.