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Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics最新文献

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A fully integrated HDD power IC with novel head retract feature 一个完全集成的硬盘电源IC与新颖的头缩回功能
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583799
R.K. Williams, A. Chang, B. Conckin, G. Pham
{"title":"A fully integrated HDD power IC with novel head retract feature","authors":"R.K. Williams, A. Chang, B. Conckin, G. Pham","doi":"10.1109/ISPSD.1994.583799","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583799","url":null,"abstract":"A fully-integrated motor-control servo power IC designed for driving small form factor hard disk drives (HDDs) is described. The \"combo chip\" IC features a novel head retract technique which eliminates the need for external Schottky diodes, yet guarantees the spindle motor's generated emf delivers uninterrupted power for emergency head retract operation. By eliminating the diode and its associated voltage drop, improved spindle motor startup current is achieved using smaller power MOSFETs. Other benefits of this approach include improved running efficiency, reduced head seek times, and increased time (and voltage margin) available to perform emergency head retract. The concept of an auxiliary supply is introduced, as is the method and motivation for eliminating the drain-to-source antiparallel diode in each of the high-side power MOSFETs.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130818356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 150 V, 320 MHz, low noise self-aligned double diffused lateral (SADDL) pnp transistor 150v, 320mhz，低噪声自对准双扩散横向(SADDL) pnp晶体管
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583815
Y. Sugawara, M. Inaba, H. Arakawa
{"title":"A 150 V, 320 MHz, low noise self-aligned double diffused lateral (SADDL) pnp transistor","authors":"Y. Sugawara, M. Inaba, H. Arakawa","doi":"10.1109/ISPSD.1994.583815","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583815","url":null,"abstract":"For realization of complementary transistors needed in high voltage, high speed analog ICs, high voltage, high performances lateral pnp transistors have been developed by utilizing the SADDL transistor structure. The developed lateral pnp transistor has a high h/sub FE/ of l00, high f/sub T/ of 320 MHz and low noise figure of 3 dB in spite of a high BV/sub CEO/ of 150 V. When BV/sub CEO/ of the developed SADDL transistor is 340 V, h/sub FE/ is 50 and f/sub T/ is 120 MHz. These f/sub T/'s are about 5 times those of the best conventional lateral pnp transistors with the same BV/sub CEO/, as reported to date.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123808659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Turn-off failure mechanisms in large (2.2 kV, 20 A) MCT devices 大型(2.2 kV, 20a) MCT器件的关断失效机制
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583724
H. Lendenmann, W. Fichtner
{"title":"Turn-off failure mechanisms in large (2.2 kV, 20 A) MCT devices","authors":"H. Lendenmann, W. Fichtner","doi":"10.1109/ISPSD.1994.583724","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583724","url":null,"abstract":"In this paper we present the phenomenological mechanisms leading to turn-off failures for large size MCT devices under inductive loading. Depending on the device current and the clamping voltage two different mechanisms lead to turn-off failures. At lower clamping voltages or in soft switching conditions the SOA is limited by the MOSFET and cathode design rules. At higher voltages and in hard switched conditions the dynamic formation of filaments limits the SOA. The failure phenomena were found to be independent, of cathode layout details, anode structuring, device size, and load circuit, thus representing the fundamental limits of the MCT. However, for optimal selection of these parameters, the failure level can be pushed to high power permitting industrial application of the device. The experimental investigation was carried out with MCT samples of different sizes and layout features and by analysis of destructed devices. The device simulator SIMUL_/sub ISE/ was used to identify the failure mechanisms.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134140816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The fast turn off advanced IGBT, a new device concept 先进的IGBT快速关断，是一种全新的器件概念
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583648
H.P. Yee, P. Lauritzen, R. Darling, M. Wakatabe, A. Sugai, K. Horiguchi
{"title":"The fast turn off advanced IGBT, a new device concept","authors":"H.P. Yee, P. Lauritzen, R. Darling, M. Wakatabe, A. Sugai, K. Horiguchi","doi":"10.1109/ISPSD.1994.583648","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583648","url":null,"abstract":"A new lateral Advanced IGBT (A-IGBT) that includes an additional P-MOSFET for faster turn-off is presented. The added P-MOSFET removes injected minority carriers in the base of A-IGBT during turn-off, achieving faster turn-off times without increasing IGBT on-state voltages. Device simulations indicate an A-IGBT has a factor of 10 improvement in turn-off time over the standard IGBT.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134239776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
2.5 kV 100 A /spl mu/-stack IGBT 2.5 kV 100a /spl mu/ stack
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583631
Y. Takahashi, T. Koga, H. Kirihata, Y. Seki
{"title":"2.5 kV 100 A /spl mu/-stack IGBT","authors":"Y. Takahashi, T. Koga, H. Kirihata, Y. Seki","doi":"10.1109/ISPSD.1994.583631","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583631","url":null,"abstract":"A 2.5 kV 100 A /spl mu/(micro)-stack IGBT has been developed. This is the first work to demonstrate the possibility of a high voltage, high current and high reliable flat-packaged MOS controlled device. The 20 mm square chip is press-contacted with an emitter electrode having four rectangular p-base regions on which the MOS gate is not arranged. The great advantage of this structure is the double side cooling and the bondingless emitter wire. The /spl mu/-stack IGBT shows the high blocking voltage of 2.5 kV, the typical saturation voltage of 3.5 V at the collector current Ic=100 A, the turn-off capability of 3/spl times/Ic, and the good pressure contact for the electrical and thermal characteristics in the range from 100 to 800 kg/chip.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133970185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
High temperature performance of dielectrically isolated LDMOSFET: characterization, simulation and analysis 介质隔离LDMOSFET的高温性能:表征、仿真与分析
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583782
R. Sunkavalli, B. J. Baliga, Y. Huang
{"title":"High temperature performance of dielectrically isolated LDMOSFET: characterization, simulation and analysis","authors":"R. Sunkavalli, B. J. Baliga, Y. Huang","doi":"10.1109/ISPSD.1994.583782","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583782","url":null,"abstract":"The temperature dependence of the static parameters of the 550 V RESURF DI LDMOSFET is reported. High temperature measurements were carried out from 25/spl deg/C-200/spl deg/C at intervals of 25/spl deg/C. The parameters measured include the on-resistance, threshold voltage, transconductance, effect of substrate bias, breakdown voltage and leakage current. Accurate analytic models, supported by extensive two-dimensional numerical simulations, have been developed to explain and predict device performance.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114069056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Critical switching condition of a non-punch-through IGBT investigated by electrothermal circuit simulation 通过电热电路仿真研究了非穿孔IGBT的临界开关条件
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583644
P. Turkes, W. Kiffe, R. Kuhnert
{"title":"Critical switching condition of a non-punch-through IGBT investigated by electrothermal circuit simulation","authors":"P. Turkes, W. Kiffe, R. Kuhnert","doi":"10.1109/ISPSD.1994.583644","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583644","url":null,"abstract":"Due to the dissipated power and the thermal impedance of the package, power devices like the IGBT are subject to significant temperature stress. This paper describes the behaviour of an IGBT within an electrical circuit, at a critical switching condition-the dynamic short. The dissipated electrical power and the resulting temperature rise are analyzed in order to get an insight into the device behaviour close to destruction. Our goal was to evaluate the simulated results in terms of the device temperature to get information about the maximum time the device can survive within this mode of operation.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121891618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high performance intelligent IGBT with overcurrent protection 具有过流保护功能的高性能智能IGBT
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583640
Y. Shimizu, Y. Nakano, Y. Kono, N. Sakurai, Y. Sugawara, S. Otaka
{"title":"A high performance intelligent IGBT with overcurrent protection","authors":"Y. Shimizu, Y. Nakano, Y. Kono, N. Sakurai, Y. Sugawara, S. Otaka","doi":"10.1109/ISPSD.1994.583640","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583640","url":null,"abstract":"We have proposed a 600 V, 30 A IGBT, having a novel overcurrent protection circuit, on one chip. The protection circuit was fabricated on a silicon wafer coated with a polycrystalline silicon film. A Zener diode was used in the gate suppress circuit to keep the gate voltage at the controlled value. An overcurrent limitation function was successfully obtained with no oscillation. The fabricated device has an on-state voltage of 1.50 V at 100 A/cm/sup 2/. The turn-off fall time is 0.28 /spl mu/s. This trade-off value is almost at the limit of this class of planer-gate IGBT.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129389898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Kirk effect limitations in high voltage IC's 柯克效应在高压集成电路中的限制
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583734
A. Ludikhuize
{"title":"Kirk effect limitations in high voltage IC's","authors":"A. Ludikhuize","doi":"10.1109/ISPSD.1994.583734","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583734","url":null,"abstract":"The voltage handling capability of Resurf LDMOS and of junction isolated islands in HV IC's is observed to decrease at high current density. This is attributed to the Kirk effect.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122545786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 86
Experimental validation of electrothermal simulations using SETIPIC for analogue integrated circuits 基于setpic的模拟集成电路电热模拟实验验证
Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics Pub Date : 1994-05-31 DOI: 10.1109/ISPSD.1994.583740
J. Ecrabey, L. Hébrard, C. Klingeihofer, F. Gaffiot, G. Jacquemod, J. Berger-Toussan, M. Le Helley
{"title":"Experimental validation of electrothermal simulations using SETIPIC for analogue integrated circuits","authors":"J. Ecrabey, L. Hébrard, C. Klingeihofer, F. Gaffiot, G. Jacquemod, J. Berger-Toussan, M. Le Helley","doi":"10.1109/ISPSD.1994.583740","DOIUrl":"https://doi.org/10.1109/ISPSD.1994.583740","url":null,"abstract":"This paper presents the validation of SETIPIC-an electrothermal simulator for power integrated circuits. SETIPIC works by alternation of electrical simulations, using a SPICE-like simulator and thermal simulations using PICMOST-a three-dimensional thermal simulator we wrote to obtain the thermal distribution on the layout surface in a transient or stationary mode. Also, an infrared thermal measurement experimental set up was built to validate SETIPIC on an industrial IC and some thermal results are given.","PeriodicalId":405897,"journal":{"name":"Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116956725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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