A 150 V, 320 MHz, low noise self-aligned double diffused lateral (SADDL) pnp transistor

Abstract

For realization of complementary transistors needed in high voltage, high speed analog ICs, high voltage, high performances lateral pnp transistors have been developed by utilizing the SADDL transistor structure. The developed lateral pnp transistor has a high h/sub FE/ of l00, high f/sub T/ of 320 MHz and low noise figure of 3 dB in spite of a high BV/sub CEO/ of 150 V. When BV/sub CEO/ of the developed SADDL transistor is 340 V, h/sub FE/ is 50 and f/sub T/ is 120 MHz. These f/sub T/'s are about 5 times those of the best conventional lateral pnp transistors with the same BV/sub CEO/, as reported to date.