N. Aburaed, A. Panthakkan, M. Al-Saad, S. Amin, W. Mansoor
{"title":"Deep Convolutional Neural Network (DCNN) for Skin Cancer Classification","authors":"N. Aburaed, A. Panthakkan, M. Al-Saad, S. Amin, W. Mansoor","doi":"10.1109/ICECS49266.2020.9294814","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294814","url":null,"abstract":"Skin cancer is one of the most threatening types of cancer, with an increasing rates throughout the decade. Detecting and classifying skin cancer in its early stages provides better chances for treatment. In the recent years, Convolutional Neural Networks (CNNs) emerged as a powerful solution that aids the diagnosis of skin cancer. In this paper, Human Against Machine (HAM) 10000 dataset is used to demonstrate skin cancer classification strategy. VGG16, VGG19, and a Deep CNN proposed in this paper are implemented, trained, and evaluated. The dataset pre-processing steps and methodology are illustrated, and the network parameters and training process are explained. The performance of all three networks are compared in terms of the average overall accuracy and loss.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125943841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Efficient Register Renaming Technique with Delayed Allocation and Register Packing","authors":"Xianhua Liu, Qinghong Yang, Miao Tao, Qinshu Chen, Xu Cheng","doi":"10.1109/ICECS49266.2020.9294955","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294955","url":null,"abstract":"Physical register file in processors needs to provide more registers when the issue width and pipeline stages increase. Expansion of the physical register file results in long access delay, larger area, and high-power consumption, which needs carefully considerations in superscalar processor design. This article designs an efficient register-renaming technique. It adopts delayed allocation and register packing techniques to improve the efficiency of physical register files temporally and spatially. Experimental results on BOOMv2 show that when the physical register file contains only 34 registers, this technology can improve the performance by 3.59-4.46 times, which achieves the peak performance with more than 64 physical registers.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125969064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors","authors":"H. Hikawa","doi":"10.1109/ICECS49266.2020.9294973","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294973","url":null,"abstract":"This paper proposes a hardware Self-Organizing Map (SOM) for high dimensional vectors. The proposed SOM is based on nested architecture with pipeline processing. Due to homogeneous modular structure, the nested architecture provides high expandability. The original nested SOM was designed to handle low-dimensional vectors with fully parallel computation, and it yielded very high performance. In this paper, the architecture is extended to handle much higher dimensional vectors by using sequential computation, which requires multiple clocks to process a single vector. To increase the performance, the proposed architecture employs pipeline computation, in which search of winner neuron and weight vector update are carried out simultaneously. Operable clock frequency for the system was 60 MHz, and its throughput reached 15012 million connection updates per second (MCUPS).","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129850940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yoann Seauve, M. Vigier, Thomas Pilloix, L. Maret, G. Sicard
{"title":"Structure of a LIFI Dedicated Binary Pixel Array","authors":"Yoann Seauve, M. Vigier, Thomas Pilloix, L. Maret, G. Sicard","doi":"10.1109/ICECS49266.2020.9294883","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294883","url":null,"abstract":"In recent years, visible light communication (VLC) have attracted a lot of attention as the key component of LIFI networks. Alongside complex and cumbersome mono LED implementations, which are used in labs to achieve extremely high data rate transmissions, slower but much more compact matrix emitters are found in the literature. In this paper, we discuss the choice of matrix architecture for data distribution and transmitter operation scheme.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"120 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129366101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Li, Xin Zhang, Yanhan Zeng, Yihan Lin, Jingci Yang, Hongzhou Tan
{"title":"High PSR output-capacitor-less LDO with double buffers technique","authors":"R. Li, Xin Zhang, Yanhan Zeng, Yihan Lin, Jingci Yang, Hongzhou Tan","doi":"10.1109/ICECS49266.2020.9294966","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294966","url":null,"abstract":"An output-capacitorless LDO regulator with double buffers technique has been proposed and simulated in a commercial 0.18µm CMOS process in this paper. To get over the tradeoff between PSR against other important design parameters such as loop stability and load capability, the proposed LDO replicates a supply ripple to the gate of pass transistor using a PMOS buffer with diode connected transistor and extends the load range by an NMOS buffer. Simulation results verify that PSR is improved effectively in the whole unity gain frequency (UGF) and the improvement is up to 40dB. In addition, the quiescent current is 33µA, providing a maximum load current of 50 mA. Besides, excellent load regulation of 2µ V/mA and line regulation of 0.06mV/V are obtained with supply from 1.2V to 2V.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130864871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shengqi Yu, R. Shafik, Thanasin Bunnam, Kaiyun Chen, Alexandre Yakovlev
{"title":"Self-Amplifying Current-Mode Multiplier Design using a Multi-Memristor Crossbar Cell Structure","authors":"Shengqi Yu, R. Shafik, Thanasin Bunnam, Kaiyun Chen, Alexandre Yakovlev","doi":"10.1109/ICECS49266.2020.9294797","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294797","url":null,"abstract":"Multipliers play a major role in modern compute-intensive applications such as artificial intelligence (AI) and signal processing. However, the logic complexity of conventional multipliers is a significant challenge for energy and performance efficiency. This paper proposes a novel current-mode multiplier without additional carry propagation and amplification circuits. The basic functional block is a one-transistor-multi-memristor (1TxM) cell, corresponding to a partial product term. In this cell, the transistor enables or disables the term by switching it ON or OFF, and the memristor acts as the resistive memory unit that determines the state of the cell: either high (i.e. logic 0) or low (i.e. logic 1). The number of memristors in a single cell is suitably chosen to achieve the required amplification depending on the significance of the cell current paths. This sidesteps the need to have a separate current mirror circuit for each path. The parallel current paths are then analogously accumulated to a common path to define the output, avoiding the complex carry propagation steps in conventional multipliers. Using Cadence Virtuoso analogue design environment, we carried out extensive experiments to confirm the functional and parametric properties of the multiplier. The results shows that the proposed multiplier reduces 64% energy cost when compared with recently proposed transistor-memristor cell based approaches.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130996687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Low Power and Smart Power Unit for Kinetic Self-Sustainable Wearable Devices","authors":"Philipp Mayer, M. Magno, L. Benini","doi":"10.1109/ICECS49266.2020.9294783","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294783","url":null,"abstract":"A novel trend to achieve long-lifetime or even self-sustainable wearable devices is to exploit energy harvesting from environmental or body energy. Their power management circuits need to be carefully designed to enable a small-size energy-efficient wearable system, supporting multiple power domains ranging from mW in an active mode to nW in sleep modes. This work presents a fully configurable smart power unit suitable for kinetic energy harvesting transducers, Kinetron MGS, enabling self-sustainability for wearable devices. The proposed power management circuit hosts a low power microcontroller to manage the energy harvesting, voltage conversion from batteries, and wake-up circuits to exit low power states automatically. The source and the load power points are decoupled with multiple DC-DC converters aiming to supply loads with adaptive voltage scaling and high reliability. Experimental results using commercial micro-kinetic generators show the flexibility and efficiency of this approach: the proposed power supply unit achieves a quiescent current of 57 nA and a maximum load current of 300 mA, delivered with a harvesting efficiency of 79 %. We evaluate the proposed system with commercial kinetic energy harvesting transducer generating 1.18 mW when worn on the ankle during walking.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130483766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Coen Arrow, J. Eshraghian, Hancong Wu, Seungbum Baek, H. Iu, K. Nazarpour
{"title":"Live Demonstration: Prosthesis Control Using a Real-Time Retina Cell Network Simulator","authors":"Coen Arrow, J. Eshraghian, Hancong Wu, Seungbum Baek, H. Iu, K. Nazarpour","doi":"10.1109/ICECS49266.2020.9294920","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294920","url":null,"abstract":"As actuated prostheses mature in reliability, they are moving beyond academic development and into market. Volitional control of the prosthesis is often by means of myoelectric signalling within the user. The corresponding electromyograph is processed by the controller, and relayed into the corresponding positions and grips. This muscle control can be impaired in amputees depending on the location of the amputation, or by neurological disorders or damage. In this demonstration we suggest a means of overcoming this limitation by using visual signalling as a control. A conductance-based retina simulator is used to demonstrate the feasibility of prosthesis control using a combination of the rod and cone cell responses.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125581799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rafael N. M. Oliveira, F. A. D. Silva, R. Reis, C. Meinhardt
{"title":"Mirror Full Adder SET Susceptibility on 7nm FinFET Technology","authors":"Rafael N. M. Oliveira, F. A. D. Silva, R. Reis, C. Meinhardt","doi":"10.1109/ICECS49266.2020.9294891","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294891","url":null,"abstract":"This work investigates the Mirror full adder circuit using a 7nm FinFET technology, considering the SET susceptibility and the robustness of all internal nodes of the circuit. This work aims to identify how this full adder topology behaves in a specific environment, observing the charge collected at each internal node. The devices involved in the processing of the carry-out function shown to be more robust than the Sum circuit and also presented a lower error rate. Furthermore, the input vector 000 proved to be the most critical one, among the input combinations, and the results show a dependence of the type of pulse in the generation of errors in the Mirror full adder.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126327345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High Input Impedance Capacitively-coupled Neural Amplifier and Its Boosting Principle","authors":"Erwin H. T. Shad, Kebria Naderi, M. Molinas","doi":"10.1109/ICECS49266.2020.9294928","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294928","url":null,"abstract":"This article proposes a technique for increasing the input impedance of conventional capacitively-coupled neural amplifiers based on careful examination of its analytical model. Following the precise derivation of the input impedance model, the effect of a negative capacitor is exploited as boosting principle to the input impedance of capacitively-coupled neural amplifiers. In order to implement this negative capacitor, some modifications were made to the conventional structure to make them suitable for capacitively-coupled neural amplifiers. The boosting factor which is calculated after these modifications exhibits frequency dependant parameters which offers further flexibility in the design and tuning. The proposed method to improve the input impedance is tested through simulation in a commercially available 0.18 µm CMOS technology. The robustness of the proposed structure is tested through Monte Carlo simulation in the presence of mismatch and process variation. Although the input impedance dropped with a factor of 2 during Monte Carlo simulations, the proposed method can still boost the input impedance by a factor of 100 at 100 Hz. While the proposed method might increase the area consumption, it maintains power efficiency property. When the proposed neural amplifier is compared to the state-of-the-art in terms of noise, power and input impedance, it shows relatively higher input impedance with negligible effect on input referred noise and power consumption which makes this structure suitable for low-power applications.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126362699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}