High PSR output-capacitor-less LDO with double buffers technique

An output-capacitorless LDO regulator with double buffers technique has been proposed and simulated in a commercial 0.18µm CMOS process in this paper. To get over the tradeoff between PSR against other important design parameters such as loop stability and load capability, the proposed LDO replicates a supply ripple to the gate of pass transistor using a PMOS buffer with diode connected transistor and extends the load range by an NMOS buffer. Simulation results verify that PSR is improved effectively in the whole unity gain frequency (UGF) and the improvement is up to 40dB. In addition, the quiescent current is 33µA, providing a maximum load current of 50 mA. Besides, excellent load regulation of 2µ V/mA and line regulation of 0.06mV/V are obtained with supply from 1.2V to 2V.