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2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献

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SCALPsim. a tool for modeling asynchronous Self-Organizing 3-D NoC architectures SCALPsim。建模异步自组织3-D NoC架构的工具
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294833
Diego Barrientos, C. Sousa, A. Upegui, B. Girau
{"title":"SCALPsim. a tool for modeling asynchronous Self-Organizing 3-D NoC architectures","authors":"Diego Barrientos, C. Sousa, A. Upegui, B. Girau","doi":"10.1109/ICECS49266.2020.9294833","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294833","url":null,"abstract":"Manycore architectures are mainly composed of a very large amount of computing nodes interconnected with a multiplicity of links usually forming a NoC-like mesh architecture. High-speed links permit to obtain a higher throughput but are much more expensive than normal links, making the interconnection of the system a cost/performance trade-off. Simulating such architectures is very important in order to characterise the optimal network topology for a given problem. In this work we introduce SCALPsim: a simulation framework permitting to evaluate routing algorithms and network properties in 1-D, 2-D and 3-D regular mesh topologies simultaneously using links of different characteristics in terms of latency and throughput. These features are particularly interesting in large scale systems with processing elements grouped into clusters, where communication properties differ largely inside and between clusters. This paper presents the framework and an application based on Cellular Self-Orzanizing Maps - CSOM.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"29 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120927427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novelty Detection in Images Using Vector Quantization with Topological Learning 基于拓扑学习的矢量量化图像新颖性检测
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294957
Yann Bernard, N. Hueber, B. Girau
{"title":"Novelty Detection in Images Using Vector Quantization with Topological Learning","authors":"Yann Bernard, N. Hueber, B. Girau","doi":"10.1109/ICECS49266.2020.9294957","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294957","url":null,"abstract":"Novelty detection is a key component of biological vision systems, where its role is to extract critical elements for the agents survival from the massive amount of information present in his visual environment. Current vision based embedded systems, such as surveillance cameras, are facing similar challenges as they have to handle a significant amount of sensory data, with limited computing power and memory bandwidth available. In order to perform artificial novelty detection in these systems, it is necessary to have a model able to learn the local visual environment without having any prior knowledge. This study explores bio-inspired unsupervised neural networks models, more precisely self-organizing maps, which are good candidates for this task. We present an original approach consisting of performing novelty detection based on vector quantization and topological learning,","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122329715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hierarchical Analog Power-Down Synthesis 分层模拟断电合成
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294889
M. Neuner, H. Graeb
{"title":"Hierarchical Analog Power-Down Synthesis","authors":"M. Neuner, H. Graeb","doi":"10.1109/ICECS49266.2020.9294889","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294889","url":null,"abstract":"Analog circuits can be switched into power-down mode to reduce their overall power consumption. State-of-the-art synthesis tools can automatically construct the power-down circuitry of such a circuit block. However, when connecting such sub-circuit blocks with each other, the correct functionality of the resulting power-down circuitry cannot be guaranteed anymore. This paper presents a new power-down synthesis method for hierarchical analog circuits. The synthesis problem is partitioned into smaller sub-problems for each individual sub-circuit block and intermediate results are reused. The proposed method is demonstrated for a high input impedance differential amplifier.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122489529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A highly linear CMOS APS circuit for column-parallel readout with improved gain and process tolerance 一种用于列并行读出的高线性CMOS APS电路，具有改进的增益和工艺公差
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294820
P. Anand, G. Arvind, Balan Bhuvan
{"title":"A highly linear CMOS APS circuit for column-parallel readout with improved gain and process tolerance","authors":"P. Anand, G. Arvind, Balan Bhuvan","doi":"10.1109/ICECS49266.2020.9294820","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294820","url":null,"abstract":"This paper presents a CMOS active pixel sensor circuit that ensures high linearity in a voltage-mode readout while exhibiting improved small-signal gain and process tolerance. The proposed circuit results in a maximum nonlinearity of 0.00013% in a 180 nm CMOS process while operating in TT corner, which is four and three orders smaller than an NMOS-input source follower and a 5-T OTA buffer, respectively. The small-signal voltage gain of our circuit is almost unity and around 25% higher than the NMOS-input source follower. The proposed circuit exhibits the least variation in its small-signal gain and linearity across corners compared to the source follower and the 5-T OTA buffer. The improvement is mainly due to the negative feedback employed in the amplifier used in the proposed circuit. The paper also presents a transistor-level placement scheme that suits the column-parallel readout architecture.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114370127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy-Efficient Start-up Dickson Charge Pump for Batteryless Biomedical Implant Devices 用于无电池生物医学植入装置的节能启动迪克森电荷泵
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294827
Kaung Oo Htet, H. Heidari, F. Moradi, R. Ghannam
{"title":"Energy-Efficient Start-up Dickson Charge Pump for Batteryless Biomedical Implant Devices","authors":"Kaung Oo Htet, H. Heidari, F. Moradi, R. Ghannam","doi":"10.1109/ICECS49266.2020.9294827","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294827","url":null,"abstract":"This paper presents a power management concept for solar energy harvesting power management using an on-chip switched-capacitor (SC) DC-DC converter for biomedical implantable applications. This design eliminates potential reversion losses caused by the switching scheme. It also mitigates the bottom plate loss by employing the charge recycling technique. Moreover, instead of using a single step clock pulse, the two-step adiabatic charge sharing clock helps reduce the energy drawn from the PV cell by 65%. Furthermore, with the help of clock disabler scheme, the power dissipation has been further reduced by disabling the entire start-up charge pump once the desired reference output voltage was reached. However, due to additional circuitry for the clock disabler, there is a tradeoff between power efficiency and power dissipation. The proposed system was implemented and fabricated in a standard 0.18-µm TSMC RF CMOS technology. The proposed converter has achieved a maximum efficiency of 73%.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129366080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Hybrid Framework for Bearing Fault Diagnosis using Physics-guided Neural Networks 基于物理引导神经网络的轴承故障诊断混合框架
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294902
L. Krupp, A. Hennig, C. Wiede, A. Grabmaier
{"title":"A Hybrid Framework for Bearing Fault Diagnosis using Physics-guided Neural Networks","authors":"L. Krupp, A. Hennig, C. Wiede, A. Grabmaier","doi":"10.1109/ICECS49266.2020.9294902","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294902","url":null,"abstract":"Emerging smart sensor systems are the main driver of innovation in many fields of application. A prominent example is condition-based monitoring and especially its subdomain fault diagnosis. The integration of advanced machine and deep learning-based signal processing into sensor systems enables new intelligent condition monitoring solutions. However, the data-based nature of machine and deep learning methods still impedes their applicability in many cases, due to a severe lack of data. In this paper, we introduce a new hybrid physics- and data-based framework aiming to solve the issue of small datasets for vibration-based fault diagnosis applied to rolling-element bearings. The framework combines a vibration simulation model and a neural network with embedded physics-based knowledge into a physics-guided neural network. Our approach aims to generate physically consistent data for the training of fault classifiers without extensive data acquisition.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of screen-printing techniques for embedding ECG sensors in medical devices 在医疗设备中嵌入心电传感器的丝网印刷技术的评价
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294914
Henry Dore, R. Aviles-Espinosa, Zhenhua Luo, Oana Anton, H. Rabe, E. Rendon-Morales
{"title":"Evaluation of screen-printing techniques for embedding ECG sensors in medical devices","authors":"Henry Dore, R. Aviles-Espinosa, Zhenhua Luo, Oana Anton, H. Rabe, E. Rendon-Morales","doi":"10.1109/ICECS49266.2020.9294914","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294914","url":null,"abstract":"Heart rate monitoring is the most important indicator to evaluate the clinical status of a newborn during birth. Approximately 90% of newborn infants make the transition from the intrauterine to extra uterine environment without major complications; however, the remaining 10% of newborn infants require assistance during this transition. Heart rate monitoring is required for guiding further interventions in the event of complications such as the need for resuscitation. In this work we evaluate the suitability of embedding electrometer-based-amplifier sensors employing novel screen-printing techniques into medical devices. We compare our results with traditional copper based wired electrodes. Our implementation was able to acquire electrocardiogram with enough signal to noise ratio, suitable for heart rate detection with a 1% loss of heart rate accuracy, compared with the copper-based electrodes. Our device has the potential to be embedded in devices for assisting births though heart rate monitoring.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129701146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interconnect Aware Power Optimization of Low Swing Driver for Multi-Chip Interfaces 面向多芯片接口的低摆幅驱动的互连感知功耗优化
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294796
Muhammad Waqas Chaudhary, A. Heinig, B. Choubey
{"title":"Interconnect Aware Power Optimization of Low Swing Driver for Multi-Chip Interfaces","authors":"Muhammad Waqas Chaudhary, A. Heinig, B. Choubey","doi":"10.1109/ICECS49266.2020.9294796","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294796","url":null,"abstract":"Communication between dies in a multi-chip system requires low power consumption. Silicon area consumed by drivers should also be minimized. Traditionally, drivers for multichip communication are designed for maximum channel loss estimated in a given system. This design strategy leads to higher power consumption even when the channel is extremely short and low loss. This paper proposes an optimization approach for interconnect aware low swing driver with a case study of source follower based architecture. It is shown that by using this strategy, the driver can reach an energy efficiency of 0.15 pJ/bit at 1 Gb/s data rate on 3.8 mm organic substrate interconnect.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130510351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs AV1和H.266/VVC视频编解码器专用硬件设计概述
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294862
Mário Saldanha, M. Corrêa, G. Corrêa, D. Palomino, M. Porto, B. Zatt, L. Agostini
{"title":"An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs","authors":"Mário Saldanha, M. Corrêa, G. Corrêa, D. Palomino, M. Porto, B. Zatt, L. Agostini","doi":"10.1109/ICECS49266.2020.9294862","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294862","url":null,"abstract":"This paper presents an overview of published works related to dedicated hardware designs for the recent AV1 codec and the H.266/VVC video coding standard. We describe the main coding tools comparing them between AV1 and H.266/VVC codecs to highlight the new algorithms and techniques employed to improve coding efficiency. Then, we present the main published works proposing FPGA/ASIC hardware designs for AV1 and H.266/VVC. It is possible to observe that most of the published works focus on the challenge of implementing the new coding tools of both codecs to attend high throughput demands, such as real-time processing of 1080p, UHD 4K and UHD 8K resolutions.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126771515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Eye Tracking Simulation for a Magnetic-based Contact Lens System 基于磁性的隐形眼镜系统眼动追踪仿真
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294969
Katarzyna Lenard, Xiangpeng Liang, Asfand Tanwear, H. Heidari
{"title":"Eye Tracking Simulation for a Magnetic-based Contact Lens System","authors":"Katarzyna Lenard, Xiangpeng Liang, Asfand Tanwear, H. Heidari","doi":"10.1109/ICECS49266.2020.9294969","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294969","url":null,"abstract":"In this paper, we present a simulation of an eye motion tracking system. The system consists of a moving magnet and three static magnetic sensors, which implies the magnet embedded in a contact lens and sensors fixed on the spectacles in the application scenario. When the eye is moving, the changing relative position between sensors and magnet will result in different sensory outputs that encodes eye movement information. The simulation of eye movements and corresponding magnetic fields was carried out in MATLAB MathWorks software. After collecting the sensory output, artificial neural network was used to decode the signal and classify the direction of gaze. In total 30 different configurations were tested to determine which one gives the highest accuracy. The network prior to each configuration was trained and the output was compared to the actual position of the eye. It was found that the lens misplacement may cause a lot of issues and requires further investigation to lower its impact on the results. This could be fixed by introducing a calibration step. For all of the configurations, usually, the confusion occurred on the neighbouring classes. This could be due to poor design of the classes, where borders of the regions do not overlap, and cause a sudden change. Based on this simulation, better tracking method can be derived.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123812193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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