Hierarchical Analog Power-Down Synthesis

Abstract

Analog circuits can be switched into power-down mode to reduce their overall power consumption. State-of-the-art synthesis tools can automatically construct the power-down circuitry of such a circuit block. However, when connecting such sub-circuit blocks with each other, the correct functionality of the resulting power-down circuitry cannot be guaranteed anymore. This paper presents a new power-down synthesis method for hierarchical analog circuits. The synthesis problem is partitioned into smaller sub-problems for each individual sub-circuit block and intermediate results are reused. The proposed method is demonstrated for a high input impedance differential amplifier.