Interconnect Aware Power Optimization of Low Swing Driver for Multi-Chip Interfaces

Communication between dies in a multi-chip system requires low power consumption. Silicon area consumed by drivers should also be minimized. Traditionally, drivers for multichip communication are designed for maximum channel loss estimated in a given system. This design strategy leads to higher power consumption even when the channel is extremely short and low loss. This paper proposes an optimization approach for interconnect aware low swing driver with a case study of source follower based architecture. It is shown that by using this strategy, the driver can reach an energy efficiency of 0.15 pJ/bit at 1 Gb/s data rate on 3.8 mm organic substrate interconnect.