2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)最新文献

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A Low-Power Multi-Frequency Chopper-Stabilized Readout with Time-Domain Delta-Sigma Modulator Suitable for Neural Recording 一种适用于神经记录的时域δ - σ调制器低功耗多频斩波稳定读出器
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294871
Mikiyoshi Mikawa, Kenta Yagi, Kazuki Itakura, Leo Onuki, N. Nakano
{"title":"A Low-Power Multi-Frequency Chopper-Stabilized Readout with Time-Domain Delta-Sigma Modulator Suitable for Neural Recording","authors":"Mikiyoshi Mikawa, Kenta Yagi, Kazuki Itakura, Leo Onuki, N. Nakano","doi":"10.1109/ICECS49266.2020.9294871","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294871","url":null,"abstract":"This paper presents a readout for multi-channel neural recording. The proposed architecture is implemented with a system-level frequency-division multiplexing technique and a time-domain delta-sigma modulator. Subthreshold region operation and the time-domain delta-sigma modulator achieves a reduction of the current dissipation. The multiplexing technique in the frequency domain enhances the power efficiency by sharing an instrumentation amplifier and the delta-sigma modulator in each channel. The proposed circuit employs a pulse-width summation technique to achieve frequency-division multiplexing in the time-domain delta-sigma modulator. The multiplexing technique of multiple frequency chopper stabilization can eliminate flicker noise and offsets. The proposed two-channel readout occupies 0.067 mm2 per channel and is designed with 0.18-µm CMOS technology. The spurious-free dynamic range is up to 50 dB in a bandwidth of 625 Hz with a low power consumption of 520 nW per channel.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121433768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Understanding and Quantifying iDS-VDSOverlap Losses in Switched-Inductor Power Supplies 理解和量化开关电感电源的ids - vd重叠损耗
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294959
G. Guérin, G. Rincón-Mora
{"title":"Understanding and Quantifying iDS-VDSOverlap Losses in Switched-Inductor Power Supplies","authors":"G. Guérin, G. Rincón-Mora","doi":"10.1109/ICECS49266.2020.9294959","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294959","url":null,"abstract":"IV-overlap power losses play an important role in the overall conversion efficiency of a switched-inductor power supply, which is why a clear understanding of its mechanism is necessary. This paper proposes an insightful model with device-based expressions. The model accounts for the non-linear and dynamic behavior of gate capacitances in switching MOSFETs and reverse-recovery effects produced by interconnected diodes, which are largely absent in the state of the art. Calculated and simulated overlap losses with and without reverse recovery are within ±10%.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131915470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memory Profiling of H.266 Versatile Video Coding Standard H.266通用视频编码标准的内存分析
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294952
Arthur Cerveira, L. Agostini, B. Zatt, F. Sampaio
{"title":"Memory Profiling of H.266 Versatile Video Coding Standard","authors":"Arthur Cerveira, L. Agostini, B. Zatt, F. Sampaio","doi":"10.1109/ICECS49266.2020.9294952","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294952","url":null,"abstract":"This work presents a profiling of the memory requirements for the encoding flow of H.266 Versatile Video Coding. The goal is to analyze the impact of each encoding module and highlight the influence of the novel coding tools introduced in H.266NVC. This profiling is performed through two sets of experiments: (1) an overall memory requirements breakdown, displaying the distribution of the accesses per encoding module, and (2) a specific assessment of the prediction steps. As results, we observed that: prediction steps perform the most memory-intensive operations in the encoding process (47 % to 58 % of all accesses); H.266/VVC novelties on transforms operations increase their memory overhead (20%, on average, of the entire encoder). Moreover, at prediction-specific evaluation, we concluded that the interpolation filters and the distortion calculations have a significant impact in the memory requirements: an average of 39% and 32% of all prediction accesses, respectively. Further, H.266/VVC novel tools on the prediction steps, such as the Affine Motion Estimation and the Geometric-Based Partitioning, do not represent major overhead on H.266NVC high memory requirements.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134250869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bio-Signal Amplifier which Maximizes the Output Voltage Amplitude using Bias Voltage Control Circuit 利用偏置电压控制电路实现输出电压幅值最大化的生物信号放大器
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294793
Takahide Sato, Keita Ogino, S. Ogawa, T. Omata
{"title":"Bio-Signal Amplifier which Maximizes the Output Voltage Amplitude using Bias Voltage Control Circuit","authors":"Takahide Sato, Keita Ogino, S. Ogawa, T. Omata","doi":"10.1109/ICECS49266.2020.9294793","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294793","url":null,"abstract":"A bio-signal amplifier whose output voltage amplitude is maximized automatically is proposed. The proposed amplifier adjusts not only the voltage gain but also the output bias voltage to maximize the output voltage amplitude. The proposed circuit is suitable for amplifying voltage signals with large spikes such as electrocardiographic signals. The proposed circuit is integrated using a 0.35 µm CMOS process, and its performances are confirmed by measurement. The measurement results show that the proposed circuit can control the output voltage amplitude by adjusting the offset and the gain.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134417892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Encapsulated Magnetoelectric Composites for Wirelessly Powered Brain Implantable Devices 用于无线供电脑植入设备的封装磁电复合材料
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294847
Eve McGlynn, Rupam Das, H. Heidari
{"title":"Encapsulated Magnetoelectric Composites for Wirelessly Powered Brain Implantable Devices","authors":"Eve McGlynn, Rupam Das, H. Heidari","doi":"10.1109/ICECS49266.2020.9294847","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294847","url":null,"abstract":"Magnetoelectric devices are readily employed as sensors, actuators, and antennas, but typically exhibit low power output. This paper presents considerations for the viability of magnetoelectric composites for wireless power transfer in neural implantation. This is accomplished herein by studying different types of biocompatible encapsulants for magnetoelectric devices, their impact on the output voltage of the composites, and the rigidity of the materials in the context of tissue damage. Simulation results indicate that a polymer encapsulant, rather than creating a substrate clamping effect, increases the voltage output of the magnetoelectric, which can be further improved by careful polymer selection. These attributes are modelled using the finite element method (FEM) with COMSOL Multiphysics. The addition of a 0.2 mm poly(ethyl acrylate) encapsulating layer increases the piezoelectric voltage to 3.77 V AC output at a magnetic field strength of 200 Oe, as the magnetostrictive layer deforms inside the flexible outer polymer. Comparing voltage conditioning circuits, the output is sufficient for low-voltage neuronal stimulation when employing a simple bridge rectifier which boasts minimal charging time and ripple voltage around 1 mV.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134554725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP 在65nm LSTP中使用薄栅氧化物器件的800MHz, 0.21 pj, 1.2V至6V电平移位器
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294984
Prakhar Shukla, Prabhat Singh, Tushar Maheshwari, Anuj Grover, V. Rana
{"title":"A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP","authors":"Prakhar Shukla, Prabhat Singh, Tushar Maheshwari, Anuj Grover, V. Rana","doi":"10.1109/ICECS49266.2020.9294984","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294984","url":null,"abstract":"In this paper, a 20T high-speed wide voltage range level shifter using thin gate oxide devices is presented. The proposed circuit is realized to shift OV to 1.2V input signal to an output swing of OV to 6V. It ensures the safe operating area limit of thin gate devices in STMicroelectronics 65nm Low Standby Power (LSTP) triple well technology. The proposed design operates at 800MHz and has a low static power consumption of 112.91nW at 1.2V input. The proposed level shifter is variation tolerant and also works at input signals down to 0.5V. This enables wide voltage range operation in dynamic voltage and frequency scaling (DVFS). The total energy dissipation per transition is measured as 0.21pJ at a capacitive load of 35fF.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133734939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Implantable Photovoltaic Energy Harvesting System with Skin Optical Analysis 具有皮肤光学分析的植入式光伏能量收集系统
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294875
Jinwei Zhao, Yang Jiang, M. Law, R. Ghannam, M. Imran, H. Heidari
{"title":"An Implantable Photovoltaic Energy Harvesting System with Skin Optical Analysis","authors":"Jinwei Zhao, Yang Jiang, M. Law, R. Ghannam, M. Imran, H. Heidari","doi":"10.1109/ICECS49266.2020.9294875","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294875","url":null,"abstract":"Medical implantable devices can use photovoltaic (PV) energy harvesting to extend battery life span and increase their performance. The power conditioning and management circuitry is essential not only to regulate the voltage requirements of the load but also optimize the output power of PV cells. However, the optical losses due to the skin and the device characteristics of the PV cells are rarely analyzed before chip fabrication. This inevitably leads to sub-optimal system performance in in-vitro or in-vivo tests owing to the varying PV output characteristics. To address this problem, we use the finite-element-method (FEM) to analyze the optical and physical performance of the PV cell under the skin, and then export the model into the p-spice simulator for circuit-level implementation. We further demonstrate a 1:2 cross-coupled DC-DC converter using pulse density modulation for load regulation control to meet the loading requirement. In this work, the PV cell can achieve an 18% of efficiency, and the power conditioning circuit can provide an 84% of end-to-end efficiency.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115533113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 16 Gbps 10:1 Serializer with Active Inductor Based CTLE for High Frequency Boosting 基于有源电感CTLE的16 Gbps 10:1串行器用于高频增强
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294949
Utkarsh Upadhyaya, Souradip Sen, Sandeep Goyal, Shalabh Gupta
{"title":"A 16 Gbps 10:1 Serializer with Active Inductor Based CTLE for High Frequency Boosting","authors":"Utkarsh Upadhyaya, Souradip Sen, Sandeep Goyal, Shalabh Gupta","doi":"10.1109/ICECS49266.2020.9294949","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294949","url":null,"abstract":"This paper presents a half-rate 8–16 Gbps 10:1 serializer with an active inductive-peaking, capacitive-degeneration (AIPCD) based continuous-time linear equalizer (CTLE) for a SerDes system. The serializer uses an efficient 5:1 multiplexer, which also serves as a generic template for a 5*N:1 serializer. The transmitter receives ten low speed 0.8/1.6 Gbps parallel PRBS-31 bit sequences and outputs a high-speed 8/16 Gbps serial data signal. The AIPCD-CTLE presented in this work outputs good discernible eye-opening for up to 18 dB of channel loss at the Nyquist frequency, which can obviate the requirement of a feedforward equalizer. Implemented in CMOS 65 nm technology, for the output data rate of 16 Gbps, the transmitter achieves a 0.33UIPP eye width at a BER of 10−12, and 16.59 dB channel loss at the Nyquist frequency with 90 mW of power consumption.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114458857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Towards Efficient and Adaptive Cyber Physical Spiking Neural Integrated Systems 迈向高效和自适应的网络物理脉冲神经集成系统
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294982
J. Madrenas, Mireya Zapata, D. Fernández, J. M. Sánchez-Chiva, Juan Valle, Diana Mata-Hernandez, Josep Angel Oltra, Jordi Cosp-Vilella, S. Sato
{"title":"Towards Efficient and Adaptive Cyber Physical Spiking Neural Integrated Systems","authors":"J. Madrenas, Mireya Zapata, D. Fernández, J. M. Sánchez-Chiva, Juan Valle, Diana Mata-Hernandez, Josep Angel Oltra, Jordi Cosp-Vilella, S. Sato","doi":"10.1109/ICECS49266.2020.9294982","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294982","url":null,"abstract":"This work introduces multi-sensor integration combined with an efficient and adaptive Spiking Neural Network (SNN) emulation architecture for local intelligent processing. For this purpose, we propose CMOS-MEMS with on-chip conditioning electronics together with spike processing by means of a real-time bioinspired and model-programmable SIMD multiprocessor. System integration considerations and results in the MEMS and processor developments are provided.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121899499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 0.8V Input Charge Pump Circuit with PVT Aware Body Bias Clock Drivers for Powering Non-Volatile Memories 一种带PVT感知体偏置时钟驱动的0.8V输入电荷泵电路,用于为非易失性存储器供电
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) Pub Date : 2020-11-23 DOI: 10.1109/ICECS49266.2020.9294932
Rohan Sinha, Rajat Kulshrestha, D. VinayN.
{"title":"A 0.8V Input Charge Pump Circuit with PVT Aware Body Bias Clock Drivers for Powering Non-Volatile Memories","authors":"Rohan Sinha, Rajat Kulshrestha, D. VinayN.","doi":"10.1109/ICECS49266.2020.9294932","DOIUrl":"https://doi.org/10.1109/ICECS49266.2020.9294932","url":null,"abstract":"This paper proposes a 0.8V input, highly efficient charge pump circuit suitable for low voltage and high output current applications in 130nm triple well CMOS process. A gate control and boosting strategy for the charge transfer switches is implemented to improve the charge transfer efficiency and voltage gain of the charge pump circuit. In addition, a PVT aware body biasing technique is applied to the transistors in the clock drivers for improving their drive strength at 0.8V supply voltage. Simulations are performed at a clock frequency of 100MHz and output current of up to 500µA. Results show higher voltage gain and power efficiency of the proposed charge pump circuit when compared with other topologies.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123961911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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