A Low-Power Multi-Frequency Chopper-Stabilized Readout with Time-Domain Delta-Sigma Modulator Suitable for Neural Recording

Abstract

This paper presents a readout for multi-channel neural recording. The proposed architecture is implemented with a system-level frequency-division multiplexing technique and a time-domain delta-sigma modulator. Subthreshold region operation and the time-domain delta-sigma modulator achieves a reduction of the current dissipation. The multiplexing technique in the frequency domain enhances the power efficiency by sharing an instrumentation amplifier and the delta-sigma modulator in each channel. The proposed circuit employs a pulse-width summation technique to achieve frequency-division multiplexing in the time-domain delta-sigma modulator. The multiplexing technique of multiple frequency chopper stabilization can eliminate flicker noise and offsets. The proposed two-channel readout occupies 0.067 mm2 per channel and is designed with 0.18-µm CMOS technology. The spurious-free dynamic range is up to 50 dB in a bandwidth of 625 Hz with a low power consumption of 520 nW per channel.