A 0.8V Input Charge Pump Circuit with PVT Aware Body Bias Clock Drivers for Powering Non-Volatile Memories

Abstract

This paper proposes a 0.8V input, highly efficient charge pump circuit suitable for low voltage and high output current applications in 130nm triple well CMOS process. A gate control and boosting strategy for the charge transfer switches is implemented to improve the charge transfer efficiency and voltage gain of the charge pump circuit. In addition, a PVT aware body biasing technique is applied to the transistors in the clock drivers for improving their drive strength at 0.8V supply voltage. Simulations are performed at a clock frequency of 100MHz and output current of up to 500µA. Results show higher voltage gain and power efficiency of the proposed charge pump circuit when compared with other topologies.