J. Madrenas, Mireya Zapata, D. Fernández, J. M. Sánchez-Chiva, Juan Valle, Diana Mata-Hernandez, Josep Angel Oltra, Jordi Cosp-Vilella, S. Sato
{"title":"Towards Efficient and Adaptive Cyber Physical Spiking Neural Integrated Systems","authors":"J. Madrenas, Mireya Zapata, D. Fernández, J. M. Sánchez-Chiva, Juan Valle, Diana Mata-Hernandez, Josep Angel Oltra, Jordi Cosp-Vilella, S. Sato","doi":"10.1109/ICECS49266.2020.9294982","DOIUrl":null,"url":null,"abstract":"This work introduces multi-sensor integration combined with an efficient and adaptive Spiking Neural Network (SNN) emulation architecture for local intelligent processing. For this purpose, we propose CMOS-MEMS with on-chip conditioning electronics together with spike processing by means of a real-time bioinspired and model-programmable SIMD multiprocessor. System integration considerations and results in the MEMS and processor developments are provided.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS49266.2020.9294982","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work introduces multi-sensor integration combined with an efficient and adaptive Spiking Neural Network (SNN) emulation architecture for local intelligent processing. For this purpose, we propose CMOS-MEMS with on-chip conditioning electronics together with spike processing by means of a real-time bioinspired and model-programmable SIMD multiprocessor. System integration considerations and results in the MEMS and processor developments are provided.