Shengqi Yu, R. Shafik, Thanasin Bunnam, Kaiyun Chen, Alexandre Yakovlev
{"title":"Self-Amplifying Current-Mode Multiplier Design using a Multi-Memristor Crossbar Cell Structure","authors":"Shengqi Yu, R. Shafik, Thanasin Bunnam, Kaiyun Chen, Alexandre Yakovlev","doi":"10.1109/ICECS49266.2020.9294797","DOIUrl":null,"url":null,"abstract":"Multipliers play a major role in modern compute-intensive applications such as artificial intelligence (AI) and signal processing. However, the logic complexity of conventional multipliers is a significant challenge for energy and performance efficiency. This paper proposes a novel current-mode multiplier without additional carry propagation and amplification circuits. The basic functional block is a one-transistor-multi-memristor (1TxM) cell, corresponding to a partial product term. In this cell, the transistor enables or disables the term by switching it ON or OFF, and the memristor acts as the resistive memory unit that determines the state of the cell: either high (i.e. logic 0) or low (i.e. logic 1). The number of memristors in a single cell is suitably chosen to achieve the required amplification depending on the significance of the cell current paths. This sidesteps the need to have a separate current mirror circuit for each path. The parallel current paths are then analogously accumulated to a common path to define the output, avoiding the complex carry propagation steps in conventional multipliers. Using Cadence Virtuoso analogue design environment, we carried out extensive experiments to confirm the functional and parametric properties of the multiplier. The results shows that the proposed multiplier reduces 64% energy cost when compared with recently proposed transistor-memristor cell based approaches.","PeriodicalId":404022,"journal":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS49266.2020.9294797","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
Multipliers play a major role in modern compute-intensive applications such as artificial intelligence (AI) and signal processing. However, the logic complexity of conventional multipliers is a significant challenge for energy and performance efficiency. This paper proposes a novel current-mode multiplier without additional carry propagation and amplification circuits. The basic functional block is a one-transistor-multi-memristor (1TxM) cell, corresponding to a partial product term. In this cell, the transistor enables or disables the term by switching it ON or OFF, and the memristor acts as the resistive memory unit that determines the state of the cell: either high (i.e. logic 0) or low (i.e. logic 1). The number of memristors in a single cell is suitably chosen to achieve the required amplification depending on the significance of the cell current paths. This sidesteps the need to have a separate current mirror circuit for each path. The parallel current paths are then analogously accumulated to a common path to define the output, avoiding the complex carry propagation steps in conventional multipliers. Using Cadence Virtuoso analogue design environment, we carried out extensive experiments to confirm the functional and parametric properties of the multiplier. The results shows that the proposed multiplier reduces 64% energy cost when compared with recently proposed transistor-memristor cell based approaches.