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Proceedings of the Ninth Asian Test Symposium最新文献

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A case study of failure analysis and guardband determination for a 64M-bit DRAM 64m位DRAM失效分析与保护带确定案例研究
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893665
Chin-Te Kao, Sam Wu, Jwu E. Chen
{"title":"A case study of failure analysis and guardband determination for a 64M-bit DRAM","authors":"Chin-Te Kao, Sam Wu, Jwu E. Chen","doi":"10.1109/ATS.2000.893665","DOIUrl":"https://doi.org/10.1109/ATS.2000.893665","url":null,"abstract":"Chips with defects, which escape the test, will cause a quality problem and will hurt goodwill and decline revenue. It is important to look for the defect root causes and to derive the prevention strategy. In this paper a case study of a 64M-DRAM is used to demonstrate the approaches of failure analysis in silicon debug stage and, consequently the determination of the tests for production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low test cost. The root cause, electrical modeling of defects, test selection and guardband determination are introduced. Finally, a quantitative measure is given to show the value of failure analysis for a high volume DRAM product.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"35 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130527737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
New built-in self-test technique based on addition/subtraction of selected node voltages 新的内置自检技术，基于所选节点电压的加/减
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893600
K. Ko, M. Wong
{"title":"New built-in self-test technique based on addition/subtraction of selected node voltages","authors":"K. Ko, M. Wong","doi":"10.1109/ATS.2000.893600","DOIUrl":"https://doi.org/10.1109/ATS.2000.893600","url":null,"abstract":"For a faulty circuit, the sensitivity of different node voltages with respect to different faults is not the same. To make use of the node voltages to detect and/or isolate faults, access to the internal circuit nodes is required. Techniques like voltage scan can be adopted to achieve this put-pose but considerable hardware overhead are incurred. Practically, not all of the circuit nodes are necessary to achieve the maximum fault coverage. In this paper we propose a new built-in self-test (BIST) technique, making use of the addition/subtraction of a small pre-selected set of circuit node voltages to achieve high fault detection and location while hardware overhead is small when compared with the voltage scan approaches.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130076170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Current status and future trend on CAD tools for VLSI testing 超大规模集成电路测试CAD工具的现状及未来趋势
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893593
Wu-Tung Cheng
{"title":"Current status and future trend on CAD tools for VLSI testing","authors":"Wu-Tung Cheng","doi":"10.1109/ATS.2000.893593","DOIUrl":"https://doi.org/10.1109/ATS.2000.893593","url":null,"abstract":"For current VLSI designs, there are two kinds of well-accepted digital testing technologies. One is for embedded memories and the other is for the logic. For embedded memories, Built-In-Self-Test (BIST) is used. For the logic, the main solutions are based on scan DFT and automatic test pattern generation (ATPG). However, to reduce the need to use an external tester, and to ease test reuse at the system level, more designs are using BIST to test logic. In the future, with system on chip (SoC) requirements and deep Sub-Micron (DSM) technologies, we believe that BIST and scan-based ATPG will continue to be the main solutions to VLSI testing. However, to be successful, some improvements are needed. The author discusses future trends in three categories: test quality, test application cost and test development effort.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata 基于一维线性混合元胞自动机的快速、低成本串行播种TPGs的设计与测试
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893653
A. Hlawiczka, M. Kopec
{"title":"Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata","authors":"A. Hlawiczka, M. Kopec","doi":"10.1109/ATS.2000.893653","DOIUrl":"https://doi.org/10.1109/ATS.2000.893653","url":null,"abstract":"The paper proposes the approach of designing CA registers that work as quick pattern generators. A new effective method of setting the initial state of such registers is presented. It is based on switching a n-cell CA register into a concatenation of p CdSR registers (Cellular Automata quasi Shift Register) each containing r cells and connected with characteristic polynomial x'. The resultant characteristic polynomial of such concatenation is p(x)=x/sup n/. Such concatenation of p registers CASR is referred as PCASR. The paper proves the possibility of setting a PCASR to any initial state by n-bit input sequence without the need of switching flip-flops into the D flip-flop mode. Moreover, it has been proven that any input sequence would be repeated at the output of a n-cell PCASR after n-clock cycle delay. Finally an effective procedure of testing PCASR is proposed.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122463968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TOF: a tool for test pattern generation optimization of an FPGA application oriented test 测试模式生成优化的一个面向FPGA应用的测试工具
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893644
M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian
{"title":"TOF: a tool for test pattern generation optimization of an FPGA application oriented test","authors":"M. Renovell, J. Portal, P. Faure, J. Figueras, Y. Zorian","doi":"10.1109/ATS.2000.893644","DOIUrl":"https://doi.org/10.1109/ATS.2000.893644","url":null,"abstract":"The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault.\" Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114899649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A realistic fault model for flash memories 一个现实的闪存故障模型
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893637
Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang
{"title":"A realistic fault model for flash memories","authors":"Yea-Ling Horng, Jing-Reng Huang, Tsin-Yuan Chang","doi":"10.1109/ATS.2000.893637","DOIUrl":"https://doi.org/10.1109/ATS.2000.893637","url":null,"abstract":"To explore all faulty behavior on NAND-type flash memory is impractical, and the defects in the SPICE model level are considered. In this paper, two SPICE models of the flash cell are developed and used for circuit-level faulty behavior simulation. The faulty behaviors can be classified to six types and applied for the fault modeling or testing of NAND-type flash memory.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An experimental analysis of spot defects in SRAMs: realistic fault models and tests sram中斑点缺陷的实验分析:现实故障模型和测试
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893615
S. Hamdioui, A. V. Goor
{"title":"An experimental analysis of spot defects in SRAMs: realistic fault models and tests","authors":"S. Hamdioui, A. V. Goor","doi":"10.1109/ATS.2000.893615","DOIUrl":"https://doi.org/10.1109/ATS.2000.893615","url":null,"abstract":"In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed into functional fault models. The existence of the usually used theoretical memory fault models will be verified and new ones will be presented. Finally, a new march test detecting all realistic faults, with a test length of 14n, will be introduced, and its fault coverage is compared with other known tests.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"442 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127799586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 127
Detection of SRAM cell stability by lowering array supply voltage 降低阵列供电电压检测SRAM电池稳定性
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893636
D. Kwai, Hung-Wen Chang, H. Liao, Ching-Hua Chiao, Yung-Fa Chou
{"title":"Detection of SRAM cell stability by lowering array supply voltage","authors":"D. Kwai, Hung-Wen Chang, H. Liao, Ching-Hua Chiao, Yung-Fa Chou","doi":"10.1109/ATS.2000.893636","DOIUrl":"https://doi.org/10.1109/ATS.2000.893636","url":null,"abstract":"In this paper, we discuss a design-for-test technique for the detection of cell stability in static random access memory (SRAM). The power supply to the memory array is isolated and independently accessible from an external terminal. By lowering the array supply voltage, the cell stability is degraded, making the defective cells susceptible to noises induced by read/write operations. On-silicon characterization result using 0.18 /spl mu/m CMOS technology is reported. It shows that the weak tailing bits in the statistical distribution can manifest themselves. The implementation of the test mode is inherently low-cost and can be combined with previously proposed methods for an improved detection capability.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116652693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A hierarchical test control architecture for core based design 基于核心设计的分层测试控制体系结构
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893633
Kuen-Jong Lee, Cheng-I Huang
{"title":"A hierarchical test control architecture for core based design","authors":"Kuen-Jong Lee, Cheng-I Huang","doi":"10.1109/ATS.2000.893633","DOIUrl":"https://doi.org/10.1109/ATS.2000.893633","url":null,"abstract":"Recently system-on-chip (SOC) design based on IP cores has become the trend of IC design. To prevent the testing problem from becoming the bottleneck of the core-based design, the IEEE P1500 Working Group is defining a test standard that can greatly simplify the core test problem. In this paper, we propose a new core-based test architecture that can support the IEEE P1500 cores as well as the well-accepted IEEE 1149.1 cores. Both the serial and parallel testing capabilities are provided. Moreover, a new hierarchical test control mechanism has been developed that facilitates the hierarchical test access for deeply embedded cores.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124154329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Fast hierarchical test path construction for DFT-free controller-datapath circuits 无dft控制器-数据路径电路的快速分层测试路径构建
Proceedings of the Ninth Asian Test Symposium Pub Date : 2000-12-04 DOI: 10.1109/ATS.2000.893623
Y. Makris, Jamison D. Collins, A. Orailoglu
{"title":"Fast hierarchical test path construction for DFT-free controller-datapath circuits","authors":"Y. Makris, Jamison D. Collins, A. Orailoglu","doi":"10.1109/ATS.2000.893623","DOIUrl":"https://doi.org/10.1109/ATS.2000.893623","url":null,"abstract":"We discuss a hierarchical test generation method for DFT-free controller-datapath pairs. A transparency based scheme is devised for the datapath, wherein locally generated vectors are translated into global design test. The controller is examined through influence tables, used to generate valid control state sequences for testing each module through hierarchical test paths. Fault coverage levels and vector counts thus attained match closely, those of traditional test generation methodologies, while sharply reducing the corresponding computational cost.","PeriodicalId":403864,"journal":{"name":"Proceedings of the Ninth Asian Test Symposium","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131539757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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